Input/Output

I/O banks and special functions

Virtex 6 devices have a very regular I/O bank structure. There are up to four I/O columns in the device:

outer left (sometimes present)
inner left (always present)
inner right (always present)
outer right (sometimes present)

These columns consist entirely of IO tiles, with one tile per two interconnect rows. Every tile contains two I/O pads: IOB0 and IOB1. IOB0 is located in the bottom row of the tile, while IOB1 is located in the top row. Every I/O bank consists of exactly one region, or 40 I/O pads. The banks are numbered as follows:

the bank in region c + i of outer left column (where c is the region containing the top half of the CFG tile) has number 15 + i
the bank in region c + i of inner left column has number 25 + i
the bank in region c + i of inner right column has number 35 + i
the bank in region c + i of outer right column has number 45 + i

All IOBs in the device are grouped into differential pairs, one pair per IO tile. IOB1 is the “true” pin of the pair, while IOB0 is the “complemented” pin. Differential input and true differential output is supported on all pins of the device.

IOB1 pads in the 8 rows surrounding the HCLK row (that is, rows 17, 19, 21, 23) are considered “clock-capable”. They can drive BUFIODQS buffers via dedicated connections. The ones in rows 19 and 21 can drive BUFR buffers in this and two surrounding regions, and are considered “multi-region clock capable”, while the ones in rows 17 and 23 are considered “single-region clock capable”. While Xilinx documentation also considers corresponding IOB0 pads clock-capable, this only means that they can be used together with IOB1 as a differential pair.

There are 8 IOB1\ s that are considered “global clock-capable” and can drive BUFGCTRL global buffers via dedicated interconnect. They are:

bank 24 rows 37, 39
bank 25 rows 1, 3
bank 34 rows 37, 39
bank 35 rows 1, 3

The IOB0 in rows 10 and 30 of every region is capable of being used as a VREF pad.

Each bank has two IOBs that can be used for reference resistors in DCI operation. They are both located in the same I/O tile, with VRP located on IOB0 and VRN located on IOB1. The relevant tile is located as follows:

bank 24: rows 4-5
bank 34: rows 0-1
banks 15, 25, 35: rows 6-7
all other banks: rows 14-15

In parallel or SPI configuration modes, some I/O pads in banks 24 and 34 are borrowed for configuration use:

bank 24 row 6: CSO_B
bank 24 row 7: RS[0]
bank 24 row 8: RS[1]
bank 24 row 9: FWE_B
bank 24 row 10: FOE_B/COPI
bank 24 row 11: FCS_B
bank 24 row 12: D[0]/FS[0]
bank 24 row 13: D[1]/FS[1]
bank 24 row 14: D[2]/FS[2]
bank 24 row 15: D[3]
bank 24 row 24: D[4]
bank 24 row 25: D[5]
bank 24 row 26: D[6]
bank 24 row 27: D[7]
bank 24 row 28: D[8]
bank 24 row 29: D[9]
bank 24 row 30: D[10]
bank 24 row 31: D[11]
bank 24 row 32: D[12]
bank 24 row 33: D[13]
bank 24 row 34: D[14]
bank 24 row 35: D[15]
bank 34 row 2: A[16]
bank 34 row 3: A[17]
bank 34 row 4: A[18]
bank 34 row 5: A[19]
bank 34 row 6: A[20]
bank 34 row 7: A[21]
bank 34 row 8: A[22]
bank 34 row 9: A[23]
bank 34 row 10: A[24]
bank 34 row 11: A[25]
bank 34 row 12: D[16]/A[0]
bank 34 row 13: D[17]/A[1]
bank 34 row 14: D[18]/A[2]
bank 34 row 15: D[19]/A[3]
bank 34 row 24: D[20]/A[4]
bank 34 row 25: D[21]/A[5]
bank 34 row 26: D[22]/A[6]
bank 34 row 27: D[23]/A[7]
bank 34 row 28: D[24]/A[8]
bank 34 row 29: D[25]/A[9]
bank 34 row 30: D[26]/A[10]
bank 34 row 31: D[27]/A[11]
bank 34 row 32: D[28]/A[12]
bank 34 row 33: D[29]/A[13]
bank 34 row 34: D[30]/A[14]
bank 34 row 35: D[31]/A[15]

The SYSMON present on the device can use up to 16 IOB pairs as auxiliary analog differential inputs. The VPx input corresponds to IOB1 and VNx corresponds to IOB0 within the same tile. If the device has a outer left IO column, the IOBs are located in banks 15 and 35; otherwise, they are located in banks 25 and 35. The IOBs are in the following tiles:

VP0/VN0: bank 35 rows 34-35
VP1/VN1: bank 35 rows 32-33
VP2/VN2: bank 35 rows 28-29
VP3/VN3: bank 35 rows 26-27
VP4/VN4: bank 35 rows 24-25
VP5/VN5: bank 35 rows 14-15
VP6/VN6: bank 35 rows 12-13
VP7/VN7: bank 35 rows 8-9
VP8/VN8: bank 15/25 rows 34-35
VP9/VN9: bank 15/25 rows 32-33
VP10/VN10: bank 15/25 rows 28-29
VP11/VN11: bank 15/25 rows 26-27
VP12/VN12: bank 15/25 rows 24-25
VP13/VN13: bank 15/25 rows 14-15
VP14/VN14: bank 15/25 rows 12-13
VP15/VN15: bank 15/25 rows 8-9

The devices also have dedicated configuration bank 0, which has no user I/O and is located in the CFG tile. It has the following pins:

CCLK
CSI_B
DIN
DONE
DOUT_BUSY
HSWAPEN
INIT_B
M0, M1, M2
PROGRAM_B
RDWR_B
TCK, TDI, TDO, TMS

Tile IO

Cells: 2

Switchbox SPEC_INT

virtex6 IO switchbox SPEC_INT permanent buffers
Destination	Source
CELL[0].IMUX_SPEC[0]	CELL[0].IMUX_IOI_OCLKDIV[0]
CELL[0].IMUX_SPEC[2]	CELL[0].IMUX_IOI_OCLK[0]
CELL[1].IMUX_SPEC[0]	CELL[1].IMUX_IOI_OCLKDIV[0]
CELL[1].IMUX_SPEC[2]	CELL[1].IMUX_IOI_OCLK[0]

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_ICLK[0]
Bits											Destination
MAIN[0][34][8]	MAIN[0][34][3]	MAIN[0][35][2]	MAIN[0][35][8]	MAIN[0][35][9]	MAIN[0][34][1]	MAIN[0][34][9]	MAIN[0][34][6]	MAIN[0][34][0]	MAIN[0][35][10]	MAIN[0][35][7]	CELL[0].IMUX_IOI_ICLK[0]	-
MAIN[1][34][55]	MAIN[1][35][55]	MAIN[1][35][60]	MAIN[1][34][61]	MAIN[1][34][53]	MAIN[1][34][56]	MAIN[1][34][54]	MAIN[1][35][62]	MAIN[1][35][54]	MAIN[1][35][57]	MAIN[1][35][63]	-	CELL[1].IMUX_IOI_ICLK[0]
											Source
0	0	0	0	0	0	0	0	0	0	0	off	off
0	0	0	1	0	0	0	0	0	0	1	CELL[0].IMUX_IMUX[14]	CELL[0].HCLK_IO[0]
0	0	0	1	0	0	0	0	0	1	0	CELL[0].IMUX_IMUX[15]	CELL[0].HCLK_IO[1]
0	0	0	1	0	0	0	0	1	0	0	CELL[0].IOCLK[3]	CELL[0].HCLK_IO[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].IOCLK[4]	CELL[0].HCLK_IO[3]
0	0	0	1	0	0	1	0	0	0	0	CELL[0].IOCLK[5]	CELL[0].HCLK_IO[4]
0	0	0	1	0	1	0	0	0	0	0	CELL[0].IOCLK[6]	CELL[0].HCLK_IO[5]
0	0	0	1	1	0	0	0	0	0	0	CELL[0].IOCLK[7]	CELL[0].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	1	CELL[0].HCLK_IO[5]	CELL[0].HCLK_IO[7]
0	0	1	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[6]	CELL[0].HCLK_IO[8]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[0]	CELL[0].HCLK_IO[9]
0	0	1	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[1]	CELL[0].HCLK_IO[10]
0	0	1	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[2]	CELL[0].HCLK_IO[11]
0	0	1	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[3]	CELL[0].RCLK_IO[0]
0	0	1	0	1	0	0	0	0	0	0	CELL[0].HCLK_IO[4]	CELL[0].RCLK_IO[1]
0	1	0	0	0	0	0	0	0	0	1	CELL[0].RCLK_IO[0]	CELL[0].RCLK_IO[2]
0	1	0	0	0	0	0	0	0	1	0	CELL[0].RCLK_IO[1]	CELL[0].RCLK_IO[3]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[7]	CELL[0].RCLK_IO[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[8]	CELL[0].RCLK_IO[5]
0	1	0	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[9]	CELL[0].IOCLK[0]
0	1	0	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[10]	CELL[0].IOCLK[1]
0	1	0	0	1	0	0	0	0	0	0	CELL[0].HCLK_IO[11]	CELL[0].IOCLK[2]
1	0	0	0	0	0	0	0	0	0	1	CELL[0].IOCLK[1]	CELL[0].IOCLK[3]
1	0	0	0	0	0	0	0	0	1	0	CELL[0].IOCLK[2]	CELL[0].IOCLK[4]
1	0	0	0	0	0	0	0	1	0	0	CELL[0].RCLK_IO[2]	CELL[0].IOCLK[5]
1	0	0	0	0	0	0	1	0	0	0	CELL[0].RCLK_IO[3]	CELL[0].IOCLK[6]
1	0	0	0	0	0	1	0	0	0	0	CELL[0].RCLK_IO[4]	CELL[0].IOCLK[7]
1	0	0	0	0	1	0	0	0	0	0	CELL[0].RCLK_IO[5]	CELL[1].IMUX_IMUX[14]
1	0	0	0	1	0	0	0	0	0	0	CELL[0].IOCLK[0]	CELL[1].IMUX_IMUX[15]

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_ICLK[1]
Bits											Destination
MAIN[0][34][39]	MAIN[0][34][34]	MAIN[0][35][33]	MAIN[0][35][39]	MAIN[0][34][38]	MAIN[0][35][40]	MAIN[0][34][32]	MAIN[0][34][37]	MAIN[0][34][31]	MAIN[0][34][41]	MAIN[0][35][35]	CELL[0].IMUX_IOI_ICLK[1]	-
MAIN[1][34][24]	MAIN[1][35][24]	MAIN[1][35][29]	MAIN[1][34][30]	MAIN[1][35][22]	MAIN[1][34][28]	MAIN[1][35][25]	MAIN[1][34][23]	MAIN[1][35][31]	MAIN[1][35][26]	MAIN[1][35][32]	-	CELL[1].IMUX_IOI_ICLK[1]
											Source
0	0	0	0	0	0	0	0	0	0	0	off	off
0	0	0	1	0	0	0	0	0	0	1	CELL[0].IMUX_IMUX[14]	CELL[0].HCLK_IO[0]
0	0	0	1	0	0	0	0	0	1	0	CELL[0].IMUX_IMUX[15]	CELL[0].HCLK_IO[1]
0	0	0	1	0	0	0	0	1	0	0	CELL[0].IOCLK[3]	CELL[0].HCLK_IO[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].IOCLK[4]	CELL[0].HCLK_IO[3]
0	0	0	1	0	0	1	0	0	0	0	CELL[0].IOCLK[5]	CELL[0].HCLK_IO[4]
0	0	0	1	0	1	0	0	0	0	0	CELL[0].IOCLK[6]	CELL[0].HCLK_IO[5]
0	0	0	1	1	0	0	0	0	0	0	CELL[0].IOCLK[7]	CELL[0].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	1	CELL[0].HCLK_IO[5]	CELL[0].HCLK_IO[7]
0	0	1	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[6]	CELL[0].HCLK_IO[8]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[0]	CELL[0].HCLK_IO[9]
0	0	1	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[1]	CELL[0].HCLK_IO[10]
0	0	1	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[2]	CELL[0].HCLK_IO[11]
0	0	1	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[3]	CELL[0].RCLK_IO[0]
0	0	1	0	1	0	0	0	0	0	0	CELL[0].HCLK_IO[4]	CELL[0].RCLK_IO[1]
0	1	0	0	0	0	0	0	0	0	1	CELL[0].RCLK_IO[0]	CELL[0].RCLK_IO[2]
0	1	0	0	0	0	0	0	0	1	0	CELL[0].RCLK_IO[1]	CELL[0].RCLK_IO[3]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[7]	CELL[0].RCLK_IO[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[8]	CELL[0].RCLK_IO[5]
0	1	0	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[9]	CELL[0].IOCLK[0]
0	1	0	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[10]	CELL[0].IOCLK[1]
0	1	0	0	1	0	0	0	0	0	0	CELL[0].HCLK_IO[11]	CELL[0].IOCLK[2]
1	0	0	0	0	0	0	0	0	0	1	CELL[0].IOCLK[1]	CELL[0].IOCLK[3]
1	0	0	0	0	0	0	0	0	1	0	CELL[0].IOCLK[2]	CELL[0].IOCLK[4]
1	0	0	0	0	0	0	0	1	0	0	CELL[0].RCLK_IO[2]	CELL[0].IOCLK[5]
1	0	0	0	0	0	0	1	0	0	0	CELL[0].RCLK_IO[3]	CELL[0].IOCLK[6]
1	0	0	0	0	0	1	0	0	0	0	CELL[0].RCLK_IO[4]	CELL[0].IOCLK[7]
1	0	0	0	0	1	0	0	0	0	0	CELL[0].RCLK_IO[5]	CELL[1].IMUX_IMUX[14]
1	0	0	0	1	0	0	0	0	0	0	CELL[0].IOCLK[0]	CELL[1].IMUX_IMUX[15]

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_OCLK[0]
Bits											Destination
MAIN[0][34][19]	MAIN[0][35][13]	MAIN[0][34][13]	MAIN[0][35][19]	MAIN[0][34][22]	MAIN[0][34][18]	MAIN[0][35][14]	MAIN[0][34][17]	MAIN[0][34][14]	MAIN[0][34][11]	MAIN[0][34][21]	CELL[0].IMUX_IOI_OCLK[0]	-
MAIN[1][34][44]	MAIN[1][35][44]	MAIN[1][34][50]	MAIN[1][35][50]	MAIN[1][35][41]	MAIN[1][35][42]	MAIN[1][35][45]	MAIN[1][34][49]	MAIN[1][35][46]	MAIN[1][35][49]	MAIN[1][35][52]	-	CELL[1].IMUX_IOI_OCLK[0]
											Source
0	0	0	0	0	0	0	0	0	0	0	off	off
0	0	0	1	0	0	0	0	0	0	1	CELL[0].IMUX_IMUX[21]	CELL[0].HCLK_IO[0]
0	0	0	1	0	0	0	0	0	1	0	CELL[0].IOCLK[3]	CELL[0].HCLK_IO[1]
0	0	0	1	0	0	0	0	1	0	0	CELL[0].IOCLK[4]	CELL[0].HCLK_IO[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].IOCLK[5]	CELL[0].HCLK_IO[3]
0	0	0	1	0	0	1	0	0	0	0	CELL[0].IOCLK[6]	CELL[0].HCLK_IO[4]
0	0	0	1	0	1	0	0	0	0	0	CELL[0].IOCLK[7]	CELL[0].HCLK_IO[5]
0	0	0	1	1	0	0	0	0	0	0	-	CELL[0].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	1	CELL[0].HCLK_IO[5]	CELL[0].HCLK_IO[7]
0	0	1	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[0]	CELL[0].HCLK_IO[8]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[1]	CELL[0].HCLK_IO[9]
0	0	1	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[2]	CELL[0].HCLK_IO[10]
0	0	1	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[3]	CELL[0].HCLK_IO[11]
0	0	1	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[4]	CELL[0].RCLK_IO[0]
0	0	1	0	1	0	0	0	0	0	0	CELL[0].HCLK_IO[6]	CELL[0].RCLK_IO[1]
0	1	0	0	0	0	0	0	0	0	1	CELL[0].RCLK_IO[0]	CELL[0].RCLK_IO[2]
0	1	0	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[7]	CELL[0].RCLK_IO[3]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[8]	CELL[0].RCLK_IO[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[9]	CELL[0].RCLK_IO[5]
0	1	0	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[10]	CELL[0].IOCLK[0]
0	1	0	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[11]	CELL[0].IOCLK[1]
0	1	0	0	1	0	0	0	0	0	0	CELL[0].RCLK_IO[1]	CELL[0].IOCLK[2]
1	0	0	0	0	0	0	0	0	0	1	CELL[0].IOCLK[1]	CELL[0].IOCLK[3]
1	0	0	0	0	0	0	0	0	1	0	CELL[0].RCLK_IO[2]	CELL[0].IOCLK[4]
1	0	0	0	0	0	0	0	1	0	0	CELL[0].RCLK_IO[3]	CELL[0].IOCLK[5]
1	0	0	0	0	0	0	1	0	0	0	CELL[0].RCLK_IO[4]	CELL[0].IOCLK[6]
1	0	0	0	0	0	1	0	0	0	0	CELL[0].RCLK_IO[5]	CELL[0].IOCLK[7]
1	0	0	0	0	1	0	0	0	0	0	CELL[0].IOCLK[0]	CELL[1].IMUX_IMUX[21]
1	0	0	0	1	0	0	0	0	0	0	CELL[0].IOCLK[2]	-

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_OCLK[1]
Bits											Destination
MAIN[0][34][50]	MAIN[0][34][45]	MAIN[0][35][44]	MAIN[0][35][50]	MAIN[0][34][53]	MAIN[0][35][48]	MAIN[0][34][52]	MAIN[0][34][48]	MAIN[0][34][42]	MAIN[0][35][47]	MAIN[0][35][43]	CELL[0].IMUX_IOI_OCLK[1]	-
MAIN[1][34][13]	MAIN[1][35][13]	MAIN[1][35][18]	MAIN[1][34][19]	MAIN[1][35][10]	MAIN[1][34][20]	MAIN[1][34][15]	MAIN[1][35][11]	MAIN[1][35][15]	MAIN[1][35][21]	MAIN[1][34][16]	-	CELL[1].IMUX_IOI_OCLK[1]
											Source
0	0	0	0	0	0	0	0	0	0	0	off	off
0	0	0	1	0	0	0	0	0	0	1	CELL[0].IMUX_IMUX[21]	CELL[0].HCLK_IO[0]
0	0	0	1	0	0	0	0	0	1	0	CELL[0].IOCLK[3]	CELL[0].HCLK_IO[1]
0	0	0	1	0	0	0	0	1	0	0	CELL[0].IOCLK[4]	CELL[0].HCLK_IO[2]
0	0	0	1	0	0	0	1	0	0	0	CELL[0].IOCLK[5]	CELL[0].HCLK_IO[3]
0	0	0	1	0	0	1	0	0	0	0	CELL[0].IOCLK[6]	CELL[0].HCLK_IO[4]
0	0	0	1	0	1	0	0	0	0	0	CELL[0].IOCLK[7]	CELL[0].HCLK_IO[5]
0	0	0	1	1	0	0	0	0	0	0	-	CELL[0].HCLK_IO[6]
0	0	1	0	0	0	0	0	0	0	1	CELL[0].HCLK_IO[5]	CELL[0].HCLK_IO[7]
0	0	1	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[0]	CELL[0].HCLK_IO[8]
0	0	1	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[1]	CELL[0].HCLK_IO[9]
0	0	1	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[2]	CELL[0].HCLK_IO[10]
0	0	1	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[3]	CELL[0].HCLK_IO[11]
0	0	1	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[4]	CELL[0].RCLK_IO[0]
0	0	1	0	1	0	0	0	0	0	0	CELL[0].HCLK_IO[6]	CELL[0].RCLK_IO[1]
0	1	0	0	0	0	0	0	0	0	1	CELL[0].RCLK_IO[0]	CELL[0].RCLK_IO[2]
0	1	0	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[7]	CELL[0].RCLK_IO[3]
0	1	0	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[8]	CELL[0].RCLK_IO[4]
0	1	0	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[9]	CELL[0].RCLK_IO[5]
0	1	0	0	0	0	1	0	0	0	0	CELL[0].HCLK_IO[10]	CELL[0].IOCLK[0]
0	1	0	0	0	1	0	0	0	0	0	CELL[0].HCLK_IO[11]	CELL[0].IOCLK[1]
0	1	0	0	1	0	0	0	0	0	0	CELL[0].RCLK_IO[1]	CELL[0].IOCLK[2]
1	0	0	0	0	0	0	0	0	0	1	CELL[0].IOCLK[1]	CELL[0].IOCLK[3]
1	0	0	0	0	0	0	0	0	1	0	CELL[0].RCLK_IO[2]	CELL[0].IOCLK[4]
1	0	0	0	0	0	0	0	1	0	0	CELL[0].RCLK_IO[3]	CELL[0].IOCLK[5]
1	0	0	0	0	0	0	1	0	0	0	CELL[0].RCLK_IO[4]	CELL[0].IOCLK[6]
1	0	0	0	0	0	1	0	0	0	0	CELL[0].RCLK_IO[5]	CELL[0].IOCLK[7]
1	0	0	0	0	1	0	0	0	0	0	CELL[0].IOCLK[0]	CELL[1].IMUX_IMUX[21]
1	0	0	0	1	0	0	0	0	0	0	CELL[0].IOCLK[2]	-

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[0]
Bits									Destination
MAIN[0][34][25]	MAIN[0][34][28]	MAIN[0][35][25]	MAIN[0][34][23]	MAIN[0][35][27]	MAIN[0][34][27]	MAIN[0][34][24]	MAIN[0][35][23]	MAIN[0][35][30]	CELL[0].IMUX_IOI_OCLKDIV[0]	-
MAIN[1][35][38]	MAIN[1][35][40]	MAIN[1][35][35]	MAIN[1][34][38]	MAIN[1][34][33]	MAIN[1][34][36]	MAIN[1][35][36]	MAIN[1][35][39]	MAIN[1][34][40]	-	CELL[1].IMUX_IOI_OCLKDIV[0]
									Source
0	0	0	0	0	0	0	0	0	off	off
0	0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[20]	CELL[0].HCLK_IO[0]
0	0	0	1	0	0	0	1	0	CELL[0].HCLK_IO[2]	CELL[0].HCLK_IO[4]
0	0	0	1	0	0	1	0	0	CELL[0].HCLK_IO[6]	CELL[0].HCLK_IO[8]
0	0	0	1	0	1	0	0	0	CELL[0].HCLK_IO[10]	CELL[0].RCLK_IO[0]
0	0	0	1	1	0	0	0	0	CELL[0].RCLK_IO[2]	CELL[0].RCLK_IO[4]
0	0	1	0	0	0	0	0	1	CELL[0].RCLK_IO[4]	CELL[0].HCLK_IO[1]
0	0	1	0	0	0	0	1	0	CELL[0].HCLK_IO[0]	CELL[0].HCLK_IO[5]
0	0	1	0	0	0	1	0	0	CELL[0].HCLK_IO[4]	CELL[0].HCLK_IO[9]
0	0	1	0	0	1	0	0	0	CELL[0].HCLK_IO[8]	CELL[0].RCLK_IO[1]
0	0	1	0	1	0	0	0	0	CELL[0].RCLK_IO[0]	CELL[0].RCLK_IO[5]
0	1	0	0	0	0	0	0	1	CELL[0].RCLK_IO[5]	CELL[0].HCLK_IO[2]
0	1	0	0	0	0	0	1	0	CELL[0].HCLK_IO[1]	CELL[0].HCLK_IO[6]
0	1	0	0	0	0	1	0	0	CELL[0].HCLK_IO[5]	CELL[0].HCLK_IO[10]
0	1	0	0	0	1	0	0	0	CELL[0].HCLK_IO[9]	CELL[0].RCLK_IO[2]
0	1	0	0	1	0	0	0	0	CELL[0].RCLK_IO[1]	CELL[1].IMUX_IMUX[20]
1	0	0	0	0	0	0	0	1	-	CELL[0].HCLK_IO[3]
1	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[3]	CELL[0].HCLK_IO[7]
1	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[7]	CELL[0].HCLK_IO[11]
1	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[11]	CELL[0].RCLK_IO[3]
1	0	0	0	1	0	0	0	0	CELL[0].RCLK_IO[3]	-

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_OCLKDIV[1]
Bits									Destination
MAIN[0][34][61]	MAIN[0][35][53]	MAIN[0][35][56]	MAIN[0][34][56]	MAIN[0][35][58]	MAIN[0][34][58]	MAIN[0][34][55]	MAIN[0][35][54]	MAIN[0][35][61]	CELL[0].IMUX_IOI_OCLKDIV[1]	-
MAIN[1][35][2]	MAIN[1][35][7]	MAIN[1][34][10]	MAIN[1][34][7]	MAIN[1][34][2]	MAIN[1][34][5]	MAIN[1][35][5]	MAIN[1][35][8]	MAIN[1][34][9]	-	CELL[1].IMUX_IOI_OCLKDIV[1]
									Source
0	0	0	0	0	0	0	0	0	off	off
0	0	0	1	0	0	0	0	1	CELL[0].IMUX_IMUX[20]	CELL[0].HCLK_IO[0]
0	0	0	1	0	0	0	1	0	CELL[0].HCLK_IO[2]	CELL[0].HCLK_IO[4]
0	0	0	1	0	0	1	0	0	CELL[0].HCLK_IO[6]	CELL[0].HCLK_IO[8]
0	0	0	1	0	1	0	0	0	CELL[0].HCLK_IO[10]	CELL[0].RCLK_IO[0]
0	0	0	1	1	0	0	0	0	CELL[0].RCLK_IO[2]	CELL[0].RCLK_IO[4]
0	0	1	0	0	0	0	0	1	CELL[0].RCLK_IO[4]	CELL[0].HCLK_IO[1]
0	0	1	0	0	0	0	1	0	CELL[0].HCLK_IO[0]	CELL[0].HCLK_IO[5]
0	0	1	0	0	0	1	0	0	CELL[0].HCLK_IO[4]	CELL[0].HCLK_IO[9]
0	0	1	0	0	1	0	0	0	CELL[0].HCLK_IO[8]	CELL[0].RCLK_IO[1]
0	0	1	0	1	0	0	0	0	CELL[0].RCLK_IO[0]	CELL[0].RCLK_IO[5]
0	1	0	0	0	0	0	0	1	CELL[0].RCLK_IO[5]	CELL[0].HCLK_IO[2]
0	1	0	0	0	0	0	1	0	CELL[0].HCLK_IO[1]	CELL[0].HCLK_IO[6]
0	1	0	0	0	0	1	0	0	CELL[0].HCLK_IO[5]	CELL[0].HCLK_IO[10]
0	1	0	0	0	1	0	0	0	CELL[0].HCLK_IO[9]	CELL[0].RCLK_IO[2]
0	1	0	0	1	0	0	0	0	CELL[0].RCLK_IO[1]	CELL[1].IMUX_IMUX[20]
1	0	0	0	0	0	0	0	1	-	CELL[0].HCLK_IO[3]
1	0	0	0	0	0	0	1	0	CELL[0].HCLK_IO[3]	CELL[0].HCLK_IO[7]
1	0	0	0	0	0	1	0	0	CELL[0].HCLK_IO[7]	CELL[0].HCLK_IO[11]
1	0	0	0	0	1	0	0	0	CELL[0].HCLK_IO[11]	CELL[0].RCLK_IO[3]
1	0	0	0	1	0	0	0	0	CELL[0].RCLK_IO[3]	-

virtex6 IO switchbox SPEC_INT muxes IMUX_IOI_OCLKPERF
Bits	Destination
MAIN[0][36][44]	CELL[0].IMUX_IOI_OCLKPERF
MAIN[1][37][19]	CELL[1].IMUX_IOI_OCLKPERF
	Source
0	CELL[0].OCLK[0]
1	CELL[0].OCLK[1]

Bels ILOGIC

virtex6 IO bel ILOGIC pins
Pin	Direction	ILOGIC[0]	ILOGIC[1]
CLK	in	CELL[0].IMUX_IOI_ICLK[0]	CELL[1].IMUX_IOI_ICLK[0]
CLKB	in	CELL[0].IMUX_IOI_ICLK[1]	CELL[1].IMUX_IOI_ICLK[1]
CLKDIV	in	CELL[0].IMUX_CLK[0] invert by MAIN[0][26][24]	CELL[1].IMUX_CLK[0] invert by MAIN[1][27][39]
SR	in	CELL[0].IMUX_CTRL[1]	CELL[1].IMUX_CTRL[1]
CE1	in	CELL[0].IMUX_IMUX[10]	CELL[1].IMUX_IMUX[10]
CE2	in	CELL[0].IMUX_IMUX[11]	CELL[1].IMUX_IMUX[11]
BITSLIP	in	CELL[0].IMUX_IMUX[8]	CELL[1].IMUX_IMUX[8]
DYNCLKSEL	in	CELL[0].IMUX_IMUX[33]	CELL[1].IMUX_IMUX[33]
DYNCLKDIVSEL	in	CELL[0].IMUX_IMUX[12]	CELL[1].IMUX_IMUX[12]
DYNOCLKSEL	in	CELL[0].IMUX_IMUX[13]	CELL[1].IMUX_IMUX[13]
O	out	CELL[0].OUT_BEL[18]	CELL[1].OUT_BEL[18]
Q1	out	CELL[0].OUT_BEL[19]	CELL[1].OUT_BEL[19]
Q2	out	CELL[0].OUT_BEL[23]	CELL[1].OUT_BEL[23]
Q3	out	CELL[0].OUT_BEL[20]	CELL[1].OUT_BEL[20]
Q4	out	CELL[0].OUT_BEL[16]	CELL[1].OUT_BEL[16]
Q5	out	CELL[0].OUT_BEL[17]	CELL[1].OUT_BEL[17]
Q6	out	CELL[0].OUT_BEL[21]	CELL[1].OUT_BEL[21]
CLKPAD	out	-	CELL[1].OUT_CLKPAD

virtex6 IO bel ILOGIC attribute bits
Attribute	ILOGIC[0]	ILOGIC[1]
CLK_INV bit 0	!MAIN[0][27][17]	!MAIN[1][26][39]
CLK_INV bit 1	!MAIN[0][27][22]	!MAIN[1][26][41]
CLK_INV bit 2	!MAIN[0][27][24]	!MAIN[1][26][46]
OCLK1_INV	!MAIN[0][27][16]	!MAIN[1][26][47]
OCLK2_INV	!MAIN[0][27][13]	!MAIN[1][26][50]
D_INV	!MAIN[0][26][0]	!MAIN[1][27][63]
DYN_CLK_INV_EN	MAIN[0][27][23]	MAIN[1][26][40]
DYN_CLKDIV_INV_EN	MAIN[0][27][9]	MAIN[1][26][54]
DYN_OCLK_INV_EN bit 0	MAIN[0][26][13]	MAIN[1][26][49]
DYN_OCLK_INV_EN bit 1	MAIN[0][27][14]	MAIN[1][27][50]
FFI1_INIT bit 0	!MAIN[0][26][52]	!MAIN[1][27][11]
FFI2_INIT bit 0	!MAIN[0][27][47]	!MAIN[1][26][16]
FFI3_INIT bit 0	!MAIN[0][27][45]	!MAIN[1][26][18]
FFI4_INIT bit 0	!MAIN[0][27][41]	!MAIN[1][26][22]
FFI1_SRVAL bit 0	!MAIN[0][26][55]	!MAIN[1][27][8]
FFI2_SRVAL bit 0	!MAIN[0][27][53]	!MAIN[1][26][10]
FFI3_SRVAL bit 0	!MAIN[0][26][41]	!MAIN[1][27][22]
FFI4_SRVAL bit 0	!MAIN[0][26][40]	!MAIN[1][27][23]
FFI_LATCH	!MAIN[0][27][55]	!MAIN[1][26][8]
FFI_SR_SYNC	MAIN[0][26][54]	MAIN[1][27][9]
FFI_SR_ENABLE	MAIN[0][27][63]	MAIN[1][26][0]
FFI_REV_ENABLE	MAIN[0][27][61]	MAIN[1][26][2]
INIT_BITSLIPCNT bit 0	!MAIN[0][27][25]	!MAIN[1][26][38]
INIT_BITSLIPCNT bit 1	!MAIN[0][26][20]	!MAIN[1][27][43]
INIT_BITSLIPCNT bit 2	!MAIN[0][27][19]	!MAIN[1][26][44]
INIT_BITSLIPCNT bit 3	!MAIN[0][26][12]	!MAIN[1][27][51]
INIT_CE bit 0	!MAIN[0][27][59]	!MAIN[1][26][4]
INIT_CE bit 1	!MAIN[0][26][60]	!MAIN[1][27][3]
INIT_RANK1_PARTIAL bit 0	!MAIN[0][27][5]	!MAIN[1][26][58]
INIT_RANK1_PARTIAL bit 1	!MAIN[0][26][6]	!MAIN[1][27][57]
INIT_RANK1_PARTIAL bit 2	!MAIN[0][26][26]	!MAIN[1][27][37]
INIT_RANK1_PARTIAL bit 3	!MAIN[0][27][27]	!MAIN[1][26][36]
INIT_RANK1_PARTIAL bit 4	!MAIN[0][27][35]	!MAIN[1][26][28]
INIT_RANK2 bit 0	!MAIN[0][27][29]	!MAIN[1][26][34]
INIT_RANK2 bit 1	!MAIN[0][27][37]	!MAIN[1][26][26]
INIT_RANK2 bit 2	!MAIN[0][27][39]	!MAIN[1][26][24]
INIT_RANK2 bit 3	!MAIN[0][26][44]	!MAIN[1][27][19]
INIT_RANK2 bit 4	!MAIN[0][26][50]	!MAIN[1][27][13]
INIT_RANK2 bit 5	!MAIN[0][27][57]	!MAIN[1][26][6]
INIT_RANK3 bit 0	!MAIN[0][26][30]	!MAIN[1][27][33]
INIT_RANK3 bit 1	!MAIN[0][26][38]	!MAIN[1][27][25]
INIT_RANK3 bit 2	!MAIN[0][26][42]	!MAIN[1][27][21]
INIT_RANK3 bit 3	!MAIN[0][26][46]	!MAIN[1][27][17]
INIT_RANK3 bit 4	!MAIN[0][27][51]	!MAIN[1][26][12]
INIT_RANK3 bit 5	!MAIN[0][26][56]	!MAIN[1][27][7]
INIT_BITSLIP bit 0	MAIN[0][26][28]	MAIN[1][27][35]
INIT_BITSLIP bit 1	MAIN[0][26][36]	MAIN[1][27][27]
INIT_BITSLIP bit 2	MAIN[0][27][43]	MAIN[1][26][20]
INIT_BITSLIP bit 3	MAIN[0][26][48]	MAIN[1][27][15]
INIT_BITSLIP bit 4	MAIN[0][27][49]	MAIN[1][26][14]
INIT_BITSLIP bit 5	MAIN[0][26][58]	MAIN[1][27][5]
I_DELAY_ENABLE	MAIN[0][27][33]	MAIN[1][26][30]
I_TSBYPASS_ENABLE	MAIN[0][26][8]	MAIN[1][27][55]
FFI_DELAY_ENABLE	MAIN[0][26][4]	MAIN[1][27][59]
FFI_TSBYPASS_ENABLE	MAIN[0][26][7]	MAIN[1][27][56]
MUX_TSBYPASS	[enum: ILOGIC_MUX_TSBYPASS]	[enum: ILOGIC_MUX_TSBYPASS]
SERDES	MAIN[0][27][54]	MAIN[1][26][9]
SERDES_MODE	[enum: IO_SERDES_MODE]	[enum: IO_SERDES_MODE]
DATA_RATE	[enum: IO_DATA_RATE]	[enum: IO_DATA_RATE]
DATA_WIDTH	[enum: IO_DATA_WIDTH]	[enum: IO_DATA_WIDTH]
INTERFACE_TYPE	[enum: ILOGIC_INTERFACE_TYPE]	[enum: ILOGIC_INTERFACE_TYPE]
NUM_CE	[enum: ILOGIC_NUM_CE]	[enum: ILOGIC_NUM_CE]
BITSLIP_ENABLE	MAIN[0][27][21]	MAIN[1][26][42]
BITSLIP_SR_SYNC	MAIN[0][27][31]	MAIN[1][26][32]
DDR_CLK_EDGE	[enum: ILOGIC_DDR_CLK_EDGE]	[enum: ILOGIC_DDR_CLK_EDGE]
RANK12_DLY	MAIN[0][26][63]	MAIN[1][27][0]
RANK23_DLY	MAIN[0][27][62]	MAIN[1][26][1]
D_EMU	MAIN[0][26][32]	MAIN[1][27][31]
D_EMU_OPTION	[enum: ILOGIC_D_EMU_OPTION]	[enum: ILOGIC_D_EMU_OPTION]
READBACK_I bit 0	MAIN[0][26][61]	MAIN[1][27][2]

virtex6 IO enum ILOGIC_MUX_TSBYPASS
ILOGIC[0].MUX_TSBYPASS	MAIN[0][26][9]
ILOGIC[1].MUX_TSBYPASS	MAIN[1][27][54]
GND	1
T	0

virtex6 IO enum IO_SERDES_MODE
ILOGIC[0].SERDES_MODE	MAIN[0][26][31]
ILOGIC[1].SERDES_MODE	MAIN[1][27][32]
MASTER	0
SLAVE	1

virtex6 IO enum IO_DATA_RATE
ILOGIC[0].DATA_RATE	MAIN[0][26][34]
ILOGIC[1].DATA_RATE	MAIN[1][27][29]
SDR	1
DDR	0

virtex6 IO enum IO_DATA_WIDTH
ILOGIC[0].DATA_WIDTH	MAIN[0][26][23]	MAIN[0][26][21]	MAIN[0][27][18]	MAIN[0][26][17]
ILOGIC[1].DATA_WIDTH	MAIN[1][27][40]	MAIN[1][27][42]	MAIN[1][26][45]	MAIN[1][27][46]
NONE	0	0	0	0
_2	0	0	1	0
_3	0	0	1	1
_4	0	1	0	0
_5	0	1	0	1
_6	0	1	1	0
_7	0	1	1	1
_8	1	0	0	0
_10	1	0	1	0

virtex6 IO enum ILOGIC_INTERFACE_TYPE
ILOGIC[0].INTERFACE_TYPE	MAIN[0][26][16]	MAIN[0][27][10]	MAIN[0][26][15]
ILOGIC[1].INTERFACE_TYPE	MAIN[1][27][47]	MAIN[1][26][53]	MAIN[1][27][48]
MEMORY	0	0	0
NETWORKING	0	0	1
OVERSAMPLE	1	0	1
MEMORY_DDR3_V6	0	1	1

virtex6 IO enum ILOGIC_NUM_CE
ILOGIC[0].NUM_CE	MAIN[0][26][62]
ILOGIC[1].NUM_CE	MAIN[1][27][1]
_1	0
_2	1

virtex6 IO enum ILOGIC_DDR_CLK_EDGE
ILOGIC[0].DDR_CLK_EDGE	MAIN[0][26][53]	MAIN[0][27][40]
ILOGIC[1].DDR_CLK_EDGE	MAIN[1][27][10]	MAIN[1][26][23]
SAME_EDGE_PIPELINED	0	0
SAME_EDGE	0	1
OPPOSITE_EDGE	1	0

virtex6 IO enum ILOGIC_D_EMU_OPTION
ILOGIC[0].D_EMU_OPTION	MAIN[0][32][62]	MAIN[0][33][63]	MAIN[0][32][63]
ILOGIC[1].D_EMU_OPTION	MAIN[1][33][1]	MAIN[1][32][0]	MAIN[1][33][0]
DLY0	0	0	1
DLY1	1	1	0
DLY2	0	1	0
DLY3	0	0	0
MATCH_DLY0	0	1	1
MATCH_DLY2	1	0	0

Bels OLOGIC

virtex6 IO bel OLOGIC pins
Pin	Direction	OLOGIC[0]	OLOGIC[1]
CLK	in	CELL[0].IMUX_IOI_OCLK[0]	CELL[1].IMUX_IOI_OCLK[0]
CLKB	in	CELL[0].IMUX_IOI_OCLK[1]	CELL[1].IMUX_IOI_OCLK[1]
CLKDIV	in	CELL[0].IMUX_IOI_OCLKDIV[0] invert by MAIN[0][32][55]	CELL[1].IMUX_IOI_OCLKDIV[0] invert by MAIN[1][33][8]
CLKDIVB	in	CELL[0].IMUX_IOI_OCLKDIV[1]	CELL[1].IMUX_IOI_OCLKDIV[1]
CLKPERF	in	CELL[0].IMUX_IOI_OCLKPERF invert by !MAIN[0][37][22]	CELL[1].IMUX_IOI_OCLKPERF invert by !MAIN[1][36][41]
SR	in	CELL[0].IMUX_CTRL[0]	CELL[1].IMUX_CTRL[0]
OCE	in	CELL[0].IMUX_IMUX[35]	CELL[1].IMUX_IMUX[35]
TCE	in	CELL[0].IMUX_IMUX[34]	CELL[1].IMUX_IMUX[34]
D1	in	CELL[0].IMUX_IMUX[42] invert by MAIN[0][33][24]	CELL[1].IMUX_IMUX[42] invert by MAIN[1][32][39]
D2	in	CELL[0].IMUX_IMUX[43] invert by MAIN[0][32][20]	CELL[1].IMUX_IMUX[43] invert by MAIN[1][33][43]
D3	in	CELL[0].IMUX_IMUX[44] invert by MAIN[0][32][14]	CELL[1].IMUX_IMUX[44] invert by MAIN[1][33][49]
D4	in	CELL[0].IMUX_IMUX[45] invert by MAIN[0][33][11]	CELL[1].IMUX_IMUX[45] invert by MAIN[1][32][52]
D5	in	CELL[0].IMUX_IMUX[46] invert by MAIN[0][32][8]	CELL[1].IMUX_IMUX[46] invert by MAIN[1][33][55]
D6	in	CELL[0].IMUX_IMUX[47] invert by MAIN[0][33][5]	CELL[1].IMUX_IMUX[47] invert by MAIN[1][32][58]
T1	in	CELL[0].IMUX_IMUX[38] invert by !MAIN[0][32][50]	CELL[1].IMUX_IMUX[38] invert by !MAIN[1][33][13]
T2	in	CELL[0].IMUX_IMUX[39] invert by !MAIN[0][33][49]	CELL[1].IMUX_IMUX[39] invert by !MAIN[1][32][14]
T3	in	CELL[0].IMUX_IMUX[40] invert by !MAIN[0][32][49]	CELL[1].IMUX_IMUX[40] invert by !MAIN[1][33][14]
T4	in	CELL[0].IMUX_IMUX[41] invert by !MAIN[0][33][48]	CELL[1].IMUX_IMUX[41] invert by !MAIN[1][32][15]
ODV	in	CELL[0].IMUX_IMUX[16]	CELL[1].IMUX_IMUX[16]
WC	in	CELL[0].IMUX_IMUX[17]	CELL[1].IMUX_IMUX[17]
TFB	out	CELL[0].OUT_BEL[22]	CELL[1].OUT_BEL[22]
IOCLKGLITCH	out	CELL[0].OUT_BEL[15]	CELL[1].OUT_BEL[15]
OCBEXTEND	out	CELL[0].OUT_BEL[5]	CELL[1].OUT_BEL[5]

virtex6 IO bel OLOGIC attribute bits
Attribute	OLOGIC[0]	OLOGIC[1]
CLK1_INV	!MAIN[0][33][55]	!MAIN[1][32][8]
CLK2_INV	!MAIN[0][32][56]	!MAIN[1][33][7]
FFO_INIT bit 0	!MAIN[0][32][39]	!MAIN[1][33][24]
FFO_RANK1_INIT bit 0	MAIN[0][32][27]	MAIN[1][33][36]
FFO_RANK1_INIT bit 1	MAIN[0][32][22]	MAIN[1][33][41]
FFO_RANK1_INIT bit 2	MAIN[0][33][16]	MAIN[1][32][47]
FFO_RANK1_INIT bit 3	MAIN[0][33][10]	MAIN[1][32][53]
FFO_RANK1_INIT bit 4	MAIN[0][33][6]	MAIN[1][32][57]
FFO_RANK1_INIT bit 5	MAIN[0][33][1]	MAIN[1][32][62]
FFO_RANK2_INIT bit 0	MAIN[0][37][56]	MAIN[1][36][7]
FFO_RANK2_INIT bit 1	MAIN[0][37][55]	MAIN[1][36][8]
FFO_RANK2_INIT bit 2	MAIN[0][36][53]	MAIN[1][37][10]
FFO_RANK2_INIT bit 3	MAIN[0][36][52]	MAIN[1][37][11]
FFO_SRVAL bit 0	!MAIN[0][32][40]	!MAIN[1][33][23]
FFO_SRVAL bit 1	!MAIN[0][33][36]	!MAIN[1][32][27]
FFO_SRVAL bit 2	!MAIN[0][32][38]	!MAIN[1][33][25]
FFO_SR_SYNC	MAIN[0][32][43]	MAIN[1][33][20]
FFO_RANK1_SR_SYNC	MAIN[0][33][0]	MAIN[1][32][63]
FFO_RANK2_SR_SYNC	MAIN[0][36][38]	MAIN[1][37][25]
FFO_LOADGEN_SR_SYNC	MAIN[0][33][19]	MAIN[1][32][44]
FFO_SR_ENABLE	MAIN[0][32][54]	MAIN[1][33][9]
V5_MUX_O	[enum: OLOGIC_V5_MUX_O]	[enum: OLOGIC_V5_MUX_O]
FFT_INIT bit 0	!MAIN[0][36][39]	!MAIN[1][37][24]
FFT_RANK1_INIT bit 0	MAIN[0][32][48]	MAIN[1][33][30]
FFT_RANK1_INIT bit 1	MAIN[0][33][42]	MAIN[1][32][26]
FFT_RANK1_INIT bit 2	MAIN[0][33][37]	MAIN[1][32][21]
FFT_RANK1_INIT bit 3	MAIN[0][32][33]	MAIN[1][33][15]
FFT_SRVAL bit 0	!MAIN[0][37][44]	!MAIN[1][36][19]
FFT_SRVAL bit 1	!MAIN[0][37][43]	!MAIN[1][36][20]
FFT_SRVAL bit 2	!MAIN[0][36][46]	!MAIN[1][37][17]
FFT_SR_SYNC	MAIN[0][36][48]	MAIN[1][37][15]
FFT_RANK1_SR_SYNC	MAIN[0][32][32]	MAIN[1][33][31]
FFT_SR_ENABLE	MAIN[0][36][50]	MAIN[1][37][13]
V5_MUX_T	[enum: OLOGIC_V5_MUX_T]	[enum: OLOGIC_V5_MUX_T]
INIT_LOADCNT bit 0	MAIN[0][32][13]	MAIN[1][33][50]
INIT_LOADCNT bit 1	MAIN[0][32][19]	MAIN[1][33][44]
INIT_LOADCNT bit 2	MAIN[0][33][23]	MAIN[1][32][40]
INIT_LOADCNT bit 3	MAIN[0][32][29]	MAIN[1][33][34]
SERDES	MAIN[0][33][31]	MAIN[1][32][32]
SERDES_MODE	[enum: IO_SERDES_MODE]	[enum: IO_SERDES_MODE]
DATA_WIDTH	[enum: IO_DATA_WIDTH]	[enum: IO_DATA_WIDTH]
TRISTATE_WIDTH	[enum: OLOGIC_TRISTATE_WIDTH]	[enum: OLOGIC_TRISTATE_WIDTH]
MISR_ENABLE	MAIN[0][27][4]	MAIN[1][26][59]
MISR_ENABLE_FDBK	MAIN[0][27][3]	MAIN[1][26][60]
MISR_RESET	MAIN[0][27][0]	MAIN[1][26][63]
MISR_CLK_SELECT	[enum: OLOGIC_MISR_CLK_SELECT]	[enum: OLOGIC_MISR_CLK_SELECT]
CLOCK_RATIO	[enum: OLOGIC_CLOCK_RATIO]	[enum: OLOGIC_CLOCK_RATIO]
SELFHEAL	MAIN[0][33][43]	MAIN[1][32][20]
DDR3_BYPASS	MAIN[0][36][23]	MAIN[1][37][40]
DDR3_DATA	MAIN[0][37][23]	MAIN[1][36][40]
WC_DELAY	MAIN[0][37][21]	MAIN[1][36][42]
ODELAY_USED	MAIN[0][36][40]	MAIN[1][37][23]
INIT_DLY_CNT bit 0	MAIN[0][36][25]	MAIN[1][37][38]
INIT_DLY_CNT bit 1	MAIN[0][37][59]	MAIN[1][36][4]
INIT_DLY_CNT bit 2	MAIN[0][37][31]	MAIN[1][36][32]
INIT_DLY_CNT bit 3	MAIN[0][37][63]	MAIN[1][36][0]
INIT_DLY_CNT bit 4	MAIN[0][36][19]	MAIN[1][37][44]
INIT_DLY_CNT bit 5	MAIN[0][37][13]	MAIN[1][36][50]
INIT_DLY_CNT bit 6	MAIN[0][37][54]	MAIN[1][36][9]
INIT_DLY_CNT bit 7	MAIN[0][36][47]	MAIN[1][37][16]
INIT_DLY_CNT bit 8	MAIN[0][36][1]	MAIN[1][37][62]
INIT_DLY_CNT bit 9	MAIN[0][36][42]	MAIN[1][37][21]
INIT_FIFO_ADDR bit 0	MAIN[0][37][20]	MAIN[1][36][43]
INIT_FIFO_ADDR bit 1	MAIN[0][37][14]	MAIN[1][36][49]
INIT_FIFO_ADDR bit 2	MAIN[0][36][12]	MAIN[1][37][51]
INIT_FIFO_ADDR bit 3	MAIN[0][36][18]	MAIN[1][37][45]
INIT_FIFO_ADDR bit 4	MAIN[0][37][46]	MAIN[1][36][17]
INIT_FIFO_ADDR bit 5	MAIN[0][36][41]	MAIN[1][37][22]
INIT_FIFO_ADDR bit 6	MAIN[0][37][39]	MAIN[1][36][24]
INIT_FIFO_ADDR bit 7	MAIN[0][36][8]	MAIN[1][37][55]
INIT_FIFO_ADDR bit 8	MAIN[0][37][2]	MAIN[1][36][61]
INIT_FIFO_ADDR bit 9	MAIN[0][36][7]	MAIN[1][37][56]
INIT_FIFO_ADDR bit 10	MAIN[0][36][0]	MAIN[1][37][63]
INIT_FIFO_RESET bit 0	MAIN[0][36][16]	MAIN[1][37][47]
INIT_FIFO_RESET bit 1	MAIN[0][37][9]	MAIN[1][36][54]
INIT_FIFO_RESET bit 2	MAIN[0][36][4]	MAIN[1][37][59]
INIT_FIFO_RESET bit 3	MAIN[0][36][21]	MAIN[1][37][42]
INIT_FIFO_RESET bit 4	MAIN[0][37][50]	MAIN[1][36][13]
INIT_FIFO_RESET bit 5	MAIN[0][36][22]	MAIN[1][37][41]
INIT_FIFO_RESET bit 6	MAIN[0][37][10]	MAIN[1][36][53]
INIT_FIFO_RESET bit 7	MAIN[0][37][33]	MAIN[1][36][30]
INIT_FIFO_RESET bit 8	MAIN[0][36][61]	MAIN[1][37][2]
INIT_FIFO_RESET bit 9	MAIN[0][36][5]	MAIN[1][37][58]
INIT_FIFO_RESET bit 10	MAIN[0][37][28]	MAIN[1][36][35]
INIT_FIFO_RESET bit 11	MAIN[0][36][56]	MAIN[1][37][7]
INIT_FIFO_RESET bit 12	MAIN[0][36][45]	MAIN[1][37][18]
INIT_PIPE_DATA0 bit 0	MAIN[0][36][29]	MAIN[1][37][34]
INIT_PIPE_DATA0 bit 1	MAIN[0][36][26]	MAIN[1][37][37]
INIT_PIPE_DATA0 bit 2	MAIN[0][37][17]	MAIN[1][36][46]
INIT_PIPE_DATA0 bit 3	MAIN[0][37][3]	MAIN[1][36][60]
INIT_PIPE_DATA0 bit 4	MAIN[0][36][11]	MAIN[1][37][52]
INIT_PIPE_DATA0 bit 5	MAIN[0][37][1]	MAIN[1][36][62]
INIT_PIPE_DATA0 bit 6	MAIN[0][32][28]	MAIN[1][33][35]
INIT_PIPE_DATA0 bit 7	MAIN[0][32][23]	MAIN[1][33][40]
INIT_PIPE_DATA0 bit 8	MAIN[0][33][17]	MAIN[1][32][46]
INIT_PIPE_DATA0 bit 9	MAIN[0][32][5]	MAIN[1][33][58]
INIT_PIPE_DATA0 bit 10	MAIN[0][33][15]	MAIN[1][32][48]
INIT_PIPE_DATA0 bit 11	MAIN[0][32][2]	MAIN[1][33][61]
INIT_PIPE_DATA1 bit 0	MAIN[0][37][34]	MAIN[1][36][29]
INIT_PIPE_DATA1 bit 1	MAIN[0][37][26]	MAIN[1][36][37]
INIT_PIPE_DATA1 bit 2	MAIN[0][37][19]	MAIN[1][36][44]
INIT_PIPE_DATA1 bit 3	MAIN[0][37][12]	MAIN[1][36][51]
INIT_PIPE_DATA1 bit 4	MAIN[0][36][15]	MAIN[1][37][48]
INIT_PIPE_DATA1 bit 5	MAIN[0][37][8]	MAIN[1][36][55]
INIT_PIPE_DATA1 bit 6	MAIN[0][33][25]	MAIN[1][32][38]
INIT_PIPE_DATA1 bit 7	MAIN[0][32][24]	MAIN[1][33][39]
INIT_PIPE_DATA1 bit 8	MAIN[0][33][20]	MAIN[1][32][43]
INIT_PIPE_DATA1 bit 9	MAIN[0][33][13]	MAIN[1][32][50]
INIT_PIPE_DATA1 bit 10	MAIN[0][33][14]	MAIN[1][32][49]
INIT_PIPE_DATA1 bit 11	MAIN[0][33][9]	MAIN[1][32][54]
INTERFACE_TYPE	[enum: OLOGIC_INTERFACE_TYPE]	[enum: OLOGIC_INTERFACE_TYPE]

virtex6 IO enum OLOGIC_V5_MUX_O
OLOGIC[0].V5_MUX_O	MAIN[0][33][57]	MAIN[0][33][58]	MAIN[0][32][25]	MAIN[0][33][26]	MAIN[0][32][58]
OLOGIC[1].V5_MUX_O	MAIN[1][32][6]	MAIN[1][32][5]	MAIN[1][33][38]	MAIN[1][32][37]	MAIN[1][33][5]
NONE	0	0	0	0	0
D1	0	0	0	0	1
SERDES_SDR	0	0	0	1	0
SERDES_DDR	0	0	1	0	0
LATCH	1	0	0	1	0
FF	0	1	0	1	0
DDR	0	1	1	0	0

virtex6 IO enum OLOGIC_V5_MUX_T
OLOGIC[0].V5_MUX_T	MAIN[0][36][62]	MAIN[0][37][61]	MAIN[0][36][60]	MAIN[0][36][59]	MAIN[0][36][63]
OLOGIC[1].V5_MUX_T	MAIN[1][37][1]	MAIN[1][36][2]	MAIN[1][37][3]	MAIN[1][37][4]	MAIN[1][37][0]
NONE	0	0	0	0	0
T1	0	0	0	0	1
SERDES_SDR	0	0	0	1	0
SERDES_DDR	0	0	1	0	0
LATCH	1	0	0	1	0
FF	0	1	0	1	0
DDR	0	1	1	0	0

virtex6 IO enum IO_SERDES_MODE
OLOGIC[0].SERDES_MODE	MAIN[0][37][32]
OLOGIC[1].SERDES_MODE	MAIN[1][36][31]
MASTER	0
SLAVE	1

virtex6 IO enum IO_DATA_WIDTH
OLOGIC[0].DATA_WIDTH	MAIN[0][32][53]	MAIN[0][33][52]	MAIN[0][32][51]	MAIN[0][33][54]	MAIN[0][33][51]	MAIN[0][32][52]	MAIN[0][33][50]	MAIN[0][33][53]
OLOGIC[1].DATA_WIDTH	MAIN[1][33][10]	MAIN[1][32][11]	MAIN[1][33][12]	MAIN[1][32][9]	MAIN[1][32][12]	MAIN[1][33][11]	MAIN[1][32][13]	MAIN[1][32][10]
NONE	0	0	0	0	0	0	0	0
_2	0	0	0	0	0	0	0	1
_3	0	0	0	0	0	0	1	0
_4	0	0	0	0	0	1	0	0
_5	0	0	0	0	1	0	0	0
_6	0	0	0	1	0	0	0	0
_7	0	0	1	0	0	0	0	0
_8	0	1	0	0	0	0	0	0
_10	1	0	0	0	0	0	0	0

virtex6 IO enum OLOGIC_TRISTATE_WIDTH
OLOGIC[0].TRISTATE_WIDTH	MAIN[0][37][49]
OLOGIC[1].TRISTATE_WIDTH	MAIN[1][36][14]
_1	0
_4	1

virtex6 IO enum OLOGIC_MISR_CLK_SELECT
OLOGIC[0].MISR_CLK_SELECT	MAIN[0][27][8]	MAIN[0][27][7]
OLOGIC[1].MISR_CLK_SELECT	MAIN[1][26][55]	MAIN[1][26][56]
NONE	0	0
CLK1	0	1
CLK2	1	0

virtex6 IO enum OLOGIC_CLOCK_RATIO
OLOGIC[0].CLOCK_RATIO	MAIN[0][33][44]	MAIN[0][32][44]	MAIN[0][33][45]	MAIN[0][32][46]
OLOGIC[1].CLOCK_RATIO	MAIN[1][32][19]	MAIN[1][33][19]	MAIN[1][32][18]	MAIN[1][33][17]
NONE	0	0	0	0
_2	0	0	0	1
_3	0	0	1	0
_4	0	0	1	1
_5	0	1	0	1
_6	1	1	0	1
_7_8	1	1	0	0

virtex6 IO enum OLOGIC_INTERFACE_TYPE
OLOGIC[0].INTERFACE_TYPE	MAIN[0][36][6]
OLOGIC[1].INTERFACE_TYPE	MAIN[1][37][57]
DEFAULT	0
MEMORY_DDR3	1

Bels IODELAY_V6

virtex6 IO bel IODELAY_V6 pins
Pin	Direction	IODELAY[0]	IODELAY[1]
C	in	CELL[0].IMUX_CLK[0] invert by MAIN[0][38][22]	CELL[1].IMUX_CLK[0] invert by MAIN[1][39][41]
CINVCTRL	in	CELL[0].IMUX_IMUX[3]	CELL[1].IMUX_IMUX[3]
CE	in	CELL[0].IMUX_IMUX[6]	CELL[1].IMUX_IMUX[6]
DATAIN	in	CELL[0].IMUX_IMUX[37] invert by !MAIN[0][38][37]	CELL[1].IMUX_IMUX[37] invert by !MAIN[1][39][26]
INC	in	CELL[0].IMUX_IMUX[7]	CELL[1].IMUX_IMUX[7]
RST	in	CELL[0].IMUX_IMUX[5]	CELL[1].IMUX_IMUX[5]
CNTVALUEIN[0]	in	CELL[0].IMUX_IMUX[1]	CELL[1].IMUX_IMUX[1]
CNTVALUEIN[1]	in	CELL[0].IMUX_IMUX[2]	CELL[1].IMUX_IMUX[2]
CNTVALUEIN[2]	in	CELL[0].IMUX_IMUX[0]	CELL[1].IMUX_IMUX[0]
CNTVALUEIN[3]	in	CELL[0].IMUX_IMUX[31]	CELL[1].IMUX_IMUX[31]
CNTVALUEIN[4]	in	CELL[0].IMUX_IMUX[36]	CELL[1].IMUX_IMUX[36]
CNTVALUEOUT[0]	out	CELL[0].OUT_BEL[10]	CELL[1].OUT_BEL[10]
CNTVALUEOUT[1]	out	CELL[0].OUT_BEL[14]	CELL[1].OUT_BEL[14]
CNTVALUEOUT[2]	out	CELL[0].OUT_BEL[13]	CELL[1].OUT_BEL[13]
CNTVALUEOUT[3]	out	CELL[0].OUT_BEL[9]	CELL[1].OUT_BEL[9]
CNTVALUEOUT[4]	out	CELL[0].OUT_BEL[12]	CELL[1].OUT_BEL[12]

virtex6 IO bel IODELAY_V6 attribute bits
Attribute	IODELAY[0]	IODELAY[1]
ENABLE	MAIN[0][37][53]	MAIN[1][36][10]
IDATAIN_INV	!MAIN[0][38][25]	!MAIN[1][39][38]
CINVCTRL_SEL	MAIN[0][38][21]	MAIN[1][39][42]
EXTRA_DELAY	MAIN[0][37][60]	MAIN[1][36][3]
DELAY_SRC	[enum: IODELAY_V6_DELAY_SRC]	[enum: IODELAY_V6_DELAY_SRC]
DELAY_TYPE	[enum: IODELAY_V6_DELAY_TYPE]	[enum: IODELAY_V6_DELAY_TYPE]
HIGH_PERFORMANCE_MODE	MAIN[0][37][45]	MAIN[1][36][18]
IDELAY_VALUE_CUR bit 0	!MAIN[0][38][27]	!MAIN[1][39][36]
IDELAY_VALUE_CUR bit 1	!MAIN[0][38][35]	!MAIN[1][39][28]
IDELAY_VALUE_CUR bit 2	!MAIN[0][38][43]	!MAIN[1][39][20]
IDELAY_VALUE_CUR bit 3	!MAIN[0][38][51]	!MAIN[1][39][12]
IDELAY_VALUE_CUR bit 4	!MAIN[0][38][57]	!MAIN[1][39][6]
IDELAY_VALUE_INIT bit 0	MAIN[0][38][20]	MAIN[1][39][43]
IDELAY_VALUE_INIT bit 1	MAIN[0][38][19]	MAIN[1][39][44]
IDELAY_VALUE_INIT bit 2	MAIN[0][38][18]	MAIN[1][39][45]
IDELAY_VALUE_INIT bit 3	MAIN[0][38][17]	MAIN[1][39][46]
IDELAY_VALUE_INIT bit 4	MAIN[0][38][16]	MAIN[1][39][47]
ALT_DELAY_VALUE bit 0	MAIN[0][38][14]	MAIN[1][39][49]
ALT_DELAY_VALUE bit 1	MAIN[0][38][13]	MAIN[1][39][50]
ALT_DELAY_VALUE bit 2	MAIN[0][38][12]	MAIN[1][39][51]
ALT_DELAY_VALUE bit 3	MAIN[0][38][11]	MAIN[1][39][52]
ALT_DELAY_VALUE bit 4	MAIN[0][38][10]	MAIN[1][39][53]

virtex6 IO enum IODELAY_V6_DELAY_SRC
IODELAY[0].DELAY_SRC	MAIN[0][38][42]	MAIN[0][38][41]	MAIN[0][38][44]	MAIN[0][38][50]	MAIN[0][38][49]
IODELAY[1].DELAY_SRC	MAIN[1][39][21]	MAIN[1][39][22]	MAIN[1][39][19]	MAIN[1][39][13]	MAIN[1][39][14]
NONE	0	0	0	0	0
I	0	0	0	0	1
IO	0	0	0	1	1
O	0	0	0	1	0
DATAIN	0	0	1	0	0
CLKIN	0	1	0	0	0
DELAYCHAIN_OSC	1	0	0	0	0

virtex6 IO enum IODELAY_V6_DELAY_TYPE
IODELAY[0].DELAY_TYPE	MAIN[0][38][52]	MAIN[0][38][9]	MAIN[0][38][8]	MAIN[0][38][15]	MAIN[0][38][26]
IODELAY[1].DELAY_TYPE	MAIN[1][39][54]	MAIN[1][39][11]	MAIN[1][39][55]	MAIN[1][39][48]	MAIN[1][39][37]
FIXED	0	0	0	0	0
VARIABLE	0	0	0	0	1
VARIABLE_SWAPPED	0	0	1	0	1
VAR_LOADABLE	0	0	0	1	1
IO_VAR_LOADABLE	1	1	1	1	1

Bels IOB

virtex6 IO bel IOB pins
Pin	Direction	IOB[0]	IOB[1]
PD_INT_EN	in	CELL[0].IMUX_IMUX[18]	CELL[1].IMUX_IMUX[18]
PU_INT_EN	in	CELL[0].IMUX_IMUX[19]	CELL[1].IMUX_IMUX[19]
KEEPER_INT_EN	in	CELL[0].IMUX_IMUX[30]	CELL[1].IMUX_IMUX[25]
DIFF_TERM_INT_EN	in	CELL[1].IMUX_IMUX[30]	-

virtex6 IO bel IOB attribute bits
Attribute	IOB[0]	IOB[1]
PULL	[enum: IOB_PULL]	[enum: IOB_PULL]
VREF_SYSMON	MAIN[0][41][3]	MAIN[1][40][60]
VR	MAIN[0][41][13]	MAIN[1][40][50]
PULL_DYNAMIC	MAIN[0][41][37]	MAIN[1][40][26]
IBUF_MODE	[enum: IOB_IBUF_MODE]	[enum: IOB_IBUF_MODE]
IBUF_VREF_HP	MAIN[0][40][2]	MAIN[1][41][61]
IBUF_DIFF_HP	MAIN[0][40][4]	MAIN[1][41][59]
OUTPUT_ENABLE bit 0	MAIN[0][40][28]	MAIN[1][40][34]
OUTPUT_ENABLE bit 1	MAIN[0][41][29]	MAIN[1][41][35]
OUTPUT_DELAY	MAIN[0][41][51]	MAIN[1][40][12]
DCI_MODE	[enum: IOB_DCI_MODE]	[enum: IOB_DCI_MODE]
DCI_MISC bit 0	MAIN[0][40][58]	MAIN[1][41][5]
DCI_MISC bit 1	MAIN[0][41][57]	MAIN[1][40][6]
DCI_T	MAIN[0][40][62]	MAIN[1][41][1]
DCIUPDATEMODE_ASREQUIRED	!MAIN[0][40][54]	!MAIN[1][41][9]
OUTPUT_PSEUDO_DIFF	MAIN[0][40][36]	-
V5_LVDS bit 0	MAIN[0][41][5]	MAIN[1][40][58]
V5_LVDS bit 1	MAIN[0][40][8]	MAIN[1][41][55]
V5_LVDS bit 2	MAIN[0][40][18]	MAIN[1][41][45]
V5_LVDS bit 3	MAIN[0][40][22]	MAIN[1][41][41]
V5_LVDS bit 4	MAIN[0][41][23]	MAIN[1][40][40]
V5_LVDS bit 5	MAIN[0][41][33]	MAIN[1][40][30]
V5_LVDS bit 6	MAIN[0][40][38]	MAIN[1][41][25]
V5_LVDS bit 7	MAIN[0][40][50]	MAIN[1][41][13]
V5_LVDS bit 8	MAIN[0][41][55]	MAIN[1][40][8]
V6_PDRIVE bit 0	!MAIN[0][40][56]	!MAIN[1][41][7]
V6_PDRIVE bit 1	!MAIN[0][40][52]	!MAIN[1][41][11]
V6_PDRIVE bit 2	!MAIN[0][41][45]	!MAIN[1][40][18]
V6_PDRIVE bit 3	MAIN[0][41][41]	MAIN[1][40][22]
V6_PDRIVE bit 4	!MAIN[0][40][26]	!MAIN[1][41][37]
V6_PDRIVE bit 5	MAIN[0][41][7]	MAIN[1][40][56]
V6_NDRIVE bit 0	!MAIN[0][41][61]	!MAIN[1][40][2]
V6_NDRIVE bit 1	!MAIN[0][41][49]	!MAIN[1][40][14]
V6_NDRIVE bit 2	!MAIN[0][40][42]	!MAIN[1][41][21]
V6_NDRIVE bit 3	!MAIN[0][40][34]	!MAIN[1][41][29]
V6_NDRIVE bit 4	MAIN[0][41][21]	MAIN[1][40][42]
V6_NDRIVE bit 5	MAIN[0][40][6]	MAIN[1][41][57]
V6_PSLEW bit 0	MAIN[0][41][39]	MAIN[1][40][24]
V6_PSLEW bit 1	MAIN[0][41][31]	MAIN[1][40][32]
V6_PSLEW bit 2	MAIN[0][41][27]	MAIN[1][40][36]
V6_PSLEW bit 3	MAIN[0][40][20]	MAIN[1][41][43]
V6_PSLEW bit 4	MAIN[0][40][10]	MAIN[1][41][53]
V6_NSLEW bit 0	MAIN[0][40][44]	MAIN[1][41][19]
V6_NSLEW bit 1	MAIN[0][40][30]	MAIN[1][41][33]
V6_NSLEW bit 2	MAIN[0][40][32]	MAIN[1][41][31]
V6_NSLEW bit 3	MAIN[0][41][17]	MAIN[1][40][46]
V6_NSLEW bit 4	MAIN[0][41][43]	MAIN[1][40][20]
V6_OUTPUT_MISC bit 0	MAIN[0][41][35]	MAIN[1][40][28]
V6_OUTPUT_MISC bit 1	MAIN[0][40][24]	MAIN[1][41][39]
V6_OUTPUT_MISC bit 2	MAIN[0][41][25]	MAIN[1][40][38]
V6_OUTPUT_MISC bit 3	MAIN[0][41][9]	MAIN[1][40][54]

virtex6 IO enum IOB_PULL
IOB[0].PULL	MAIN[0][40][48]	MAIN[0][41][47]	MAIN[0][40][46]
IOB[1].PULL	MAIN[1][41][15]	MAIN[1][40][16]	MAIN[1][41][17]
NONE	0	0	1
PULLUP	0	1	1
PULLDOWN	0	0	0
KEEPER	1	0	1

virtex6 IO enum IOB_IBUF_MODE
IOB[0].IBUF_MODE	MAIN[0][41][63]	MAIN[0][41][1]	MAIN[0][40][0]
IOB[1].IBUF_MODE	MAIN[1][40][0]	MAIN[1][40][62]	MAIN[1][41][63]
NONE	0	0	0
VREF	0	0	1
DIFF	0	1	0
CMOS	1	1	1
CMOS12	0	1	1

virtex6 IO enum IOB_DCI_MODE
IOB[0].DCI_MODE	MAIN[0][41][19]	MAIN[0][40][12]	MAIN[0][40][14]
IOB[1].DCI_MODE	MAIN[1][40][44]	MAIN[1][41][51]	MAIN[1][41][49]
NONE	0	0	0
OUTPUT	0	0	1
OUTPUT_HALF	0	1	0
TERM_VCC	0	1	1
TERM_SPLIT	1	0	0

Bel wires

virtex6 IO bel wires
Wire	Pins
CELL[0].IMUX_CLK[0]	ILOGIC[0].CLKDIV, IODELAY[0].C
CELL[0].IMUX_CTRL[0]	OLOGIC[0].SR
CELL[0].IMUX_CTRL[1]	ILOGIC[0].SR
CELL[0].IMUX_IMUX[0]	IODELAY[0].CNTVALUEIN[2]
CELL[0].IMUX_IMUX[1]	IODELAY[0].CNTVALUEIN[0]
CELL[0].IMUX_IMUX[2]	IODELAY[0].CNTVALUEIN[1]
CELL[0].IMUX_IMUX[3]	IODELAY[0].CINVCTRL
CELL[0].IMUX_IMUX[5]	IODELAY[0].RST
CELL[0].IMUX_IMUX[6]	IODELAY[0].CE
CELL[0].IMUX_IMUX[7]	IODELAY[0].INC
CELL[0].IMUX_IMUX[8]	ILOGIC[0].BITSLIP
CELL[0].IMUX_IMUX[10]	ILOGIC[0].CE1
CELL[0].IMUX_IMUX[11]	ILOGIC[0].CE2
CELL[0].IMUX_IMUX[12]	ILOGIC[0].DYNCLKDIVSEL
CELL[0].IMUX_IMUX[13]	ILOGIC[0].DYNOCLKSEL
CELL[0].IMUX_IMUX[16]	OLOGIC[0].ODV
CELL[0].IMUX_IMUX[17]	OLOGIC[0].WC
CELL[0].IMUX_IMUX[18]	IOB[0].PD_INT_EN
CELL[0].IMUX_IMUX[19]	IOB[0].PU_INT_EN
CELL[0].IMUX_IMUX[30]	IOB[0].KEEPER_INT_EN
CELL[0].IMUX_IMUX[31]	IODELAY[0].CNTVALUEIN[3]
CELL[0].IMUX_IMUX[33]	ILOGIC[0].DYNCLKSEL
CELL[0].IMUX_IMUX[34]	OLOGIC[0].TCE
CELL[0].IMUX_IMUX[35]	OLOGIC[0].OCE
CELL[0].IMUX_IMUX[36]	IODELAY[0].CNTVALUEIN[4]
CELL[0].IMUX_IMUX[37]	IODELAY[0].DATAIN
CELL[0].IMUX_IMUX[38]	OLOGIC[0].T1
CELL[0].IMUX_IMUX[39]	OLOGIC[0].T2
CELL[0].IMUX_IMUX[40]	OLOGIC[0].T3
CELL[0].IMUX_IMUX[41]	OLOGIC[0].T4
CELL[0].IMUX_IMUX[42]	OLOGIC[0].D1
CELL[0].IMUX_IMUX[43]	OLOGIC[0].D2
CELL[0].IMUX_IMUX[44]	OLOGIC[0].D3
CELL[0].IMUX_IMUX[45]	OLOGIC[0].D4
CELL[0].IMUX_IMUX[46]	OLOGIC[0].D5
CELL[0].IMUX_IMUX[47]	OLOGIC[0].D6
CELL[0].OUT_BEL[5]	OLOGIC[0].OCBEXTEND
CELL[0].OUT_BEL[9]	IODELAY[0].CNTVALUEOUT[3]
CELL[0].OUT_BEL[10]	IODELAY[0].CNTVALUEOUT[0]
CELL[0].OUT_BEL[12]	IODELAY[0].CNTVALUEOUT[4]
CELL[0].OUT_BEL[13]	IODELAY[0].CNTVALUEOUT[2]
CELL[0].OUT_BEL[14]	IODELAY[0].CNTVALUEOUT[1]
CELL[0].OUT_BEL[15]	OLOGIC[0].IOCLKGLITCH
CELL[0].OUT_BEL[16]	ILOGIC[0].Q4
CELL[0].OUT_BEL[17]	ILOGIC[0].Q5
CELL[0].OUT_BEL[18]	ILOGIC[0].O
CELL[0].OUT_BEL[19]	ILOGIC[0].Q1
CELL[0].OUT_BEL[20]	ILOGIC[0].Q3
CELL[0].OUT_BEL[21]	ILOGIC[0].Q6
CELL[0].OUT_BEL[22]	OLOGIC[0].TFB
CELL[0].OUT_BEL[23]	ILOGIC[0].Q2
CELL[0].IMUX_IOI_ICLK[0]	ILOGIC[0].CLK
CELL[0].IMUX_IOI_ICLK[1]	ILOGIC[0].CLKB
CELL[0].IMUX_IOI_OCLK[0]	OLOGIC[0].CLK
CELL[0].IMUX_IOI_OCLK[1]	OLOGIC[0].CLKB
CELL[0].IMUX_IOI_OCLKDIV[0]	OLOGIC[0].CLKDIV
CELL[0].IMUX_IOI_OCLKDIV[1]	OLOGIC[0].CLKDIVB
CELL[0].IMUX_IOI_OCLKPERF	OLOGIC[0].CLKPERF
CELL[1].IMUX_CLK[0]	ILOGIC[1].CLKDIV, IODELAY[1].C
CELL[1].IMUX_CTRL[0]	OLOGIC[1].SR
CELL[1].IMUX_CTRL[1]	ILOGIC[1].SR
CELL[1].IMUX_IMUX[0]	IODELAY[1].CNTVALUEIN[2]
CELL[1].IMUX_IMUX[1]	IODELAY[1].CNTVALUEIN[0]
CELL[1].IMUX_IMUX[2]	IODELAY[1].CNTVALUEIN[1]
CELL[1].IMUX_IMUX[3]	IODELAY[1].CINVCTRL
CELL[1].IMUX_IMUX[5]	IODELAY[1].RST
CELL[1].IMUX_IMUX[6]	IODELAY[1].CE
CELL[1].IMUX_IMUX[7]	IODELAY[1].INC
CELL[1].IMUX_IMUX[8]	ILOGIC[1].BITSLIP
CELL[1].IMUX_IMUX[10]	ILOGIC[1].CE1
CELL[1].IMUX_IMUX[11]	ILOGIC[1].CE2
CELL[1].IMUX_IMUX[12]	ILOGIC[1].DYNCLKDIVSEL
CELL[1].IMUX_IMUX[13]	ILOGIC[1].DYNOCLKSEL
CELL[1].IMUX_IMUX[16]	OLOGIC[1].ODV
CELL[1].IMUX_IMUX[17]	OLOGIC[1].WC
CELL[1].IMUX_IMUX[18]	IOB[1].PD_INT_EN
CELL[1].IMUX_IMUX[19]	IOB[1].PU_INT_EN
CELL[1].IMUX_IMUX[25]	IOB[1].KEEPER_INT_EN
CELL[1].IMUX_IMUX[30]	IOB[0].DIFF_TERM_INT_EN
CELL[1].IMUX_IMUX[31]	IODELAY[1].CNTVALUEIN[3]
CELL[1].IMUX_IMUX[33]	ILOGIC[1].DYNCLKSEL
CELL[1].IMUX_IMUX[34]	OLOGIC[1].TCE
CELL[1].IMUX_IMUX[35]	OLOGIC[1].OCE
CELL[1].IMUX_IMUX[36]	IODELAY[1].CNTVALUEIN[4]
CELL[1].IMUX_IMUX[37]	IODELAY[1].DATAIN
CELL[1].IMUX_IMUX[38]	OLOGIC[1].T1
CELL[1].IMUX_IMUX[39]	OLOGIC[1].T2
CELL[1].IMUX_IMUX[40]	OLOGIC[1].T3
CELL[1].IMUX_IMUX[41]	OLOGIC[1].T4
CELL[1].IMUX_IMUX[42]	OLOGIC[1].D1
CELL[1].IMUX_IMUX[43]	OLOGIC[1].D2
CELL[1].IMUX_IMUX[44]	OLOGIC[1].D3
CELL[1].IMUX_IMUX[45]	OLOGIC[1].D4
CELL[1].IMUX_IMUX[46]	OLOGIC[1].D5
CELL[1].IMUX_IMUX[47]	OLOGIC[1].D6
CELL[1].OUT_BEL[5]	OLOGIC[1].OCBEXTEND
CELL[1].OUT_BEL[9]	IODELAY[1].CNTVALUEOUT[3]
CELL[1].OUT_BEL[10]	IODELAY[1].CNTVALUEOUT[0]
CELL[1].OUT_BEL[12]	IODELAY[1].CNTVALUEOUT[4]
CELL[1].OUT_BEL[13]	IODELAY[1].CNTVALUEOUT[2]
CELL[1].OUT_BEL[14]	IODELAY[1].CNTVALUEOUT[1]
CELL[1].OUT_BEL[15]	OLOGIC[1].IOCLKGLITCH
CELL[1].OUT_BEL[16]	ILOGIC[1].Q4
CELL[1].OUT_BEL[17]	ILOGIC[1].Q5
CELL[1].OUT_BEL[18]	ILOGIC[1].O
CELL[1].OUT_BEL[19]	ILOGIC[1].Q1
CELL[1].OUT_BEL[20]	ILOGIC[1].Q3
CELL[1].OUT_BEL[21]	ILOGIC[1].Q6
CELL[1].OUT_BEL[22]	OLOGIC[1].TFB
CELL[1].OUT_BEL[23]	ILOGIC[1].Q2
CELL[1].OUT_CLKPAD	ILOGIC[1].CLKPAD
CELL[1].IMUX_IOI_ICLK[0]	ILOGIC[1].CLK
CELL[1].IMUX_IOI_ICLK[1]	ILOGIC[1].CLKB
CELL[1].IMUX_IOI_OCLK[0]	OLOGIC[1].CLK
CELL[1].IMUX_IOI_OCLK[1]	OLOGIC[1].CLKB
CELL[1].IMUX_IOI_OCLKDIV[0]	OLOGIC[1].CLKDIV
CELL[1].IMUX_IOI_OCLKDIV[1]	OLOGIC[1].CLKDIVB
CELL[1].IMUX_IOI_OCLKPERF	OLOGIC[1].CLKPERF

Bitstream

virtex6 IO rect MAIN[0]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: RANK12_DLY	ILOGIC[0]: FFI_SR_ENABLE	-	-	-	-	ILOGIC[0]: D_EMU_OPTION bit 0	ILOGIC[0]: D_EMU_OPTION bit 1	-	-	OLOGIC[0]: V5_MUX_T bit 0	OLOGIC[0]: INIT_DLY_CNT bit 3	-	-	-	IOB[0]: IBUF_MODE bit 2	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: NUM_CE bit 0	ILOGIC[0]: RANK23_DLY	-	-	-	-	ILOGIC[0]: D_EMU_OPTION bit 2	-	-	-	OLOGIC[0]: V5_MUX_T bit 4	-	-	-	IOB[0]: DCI_T	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: READBACK_I bit 0	ILOGIC[0]: FFI_REV_ENABLE	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 8	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 0	OLOGIC[0]: INIT_FIFO_RESET bit 8	OLOGIC[0]: V5_MUX_T bit 3	-	-	-	IOB[0]: ! V6_NDRIVE bit 0	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_CE bit 1	-	-	-	-	-	-	-	-	-	OLOGIC[0]: V5_MUX_T bit 2	IODELAY[0]: EXTRA_DELAY	-	-	-	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_CE bit 0	-	-	-	-	-	-	-	-	OLOGIC[0]: V5_MUX_T bit 1	OLOGIC[0]: INIT_DLY_CNT bit 1	-	-	-	-	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INIT_BITSLIP bit 5	-	-	-	-	-	OLOGIC[0]: V5_MUX_O bit 0	OLOGIC[0]: V5_MUX_O bit 3	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 3	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 4	-	-	-	-	IOB[0]: DCI_MISC bit 0	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK2 bit 5	-	-	-	-	-	OLOGIC[0]: V5_MUX_O bit 4	-	-	-	-	IODELAY[0]: ! IDELAY_VALUE_CUR bit 4	-	-	IOB[0]: DCI_MISC bit 1	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK3 bit 5	-	-	-	-	-	OLOGIC[0]: ! CLK2_INV	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 5	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 6	OLOGIC[0]: INIT_FIFO_RESET bit 11	OLOGIC[0]: FFO_RANK2_INIT bit 0	-	-	IOB[0]: ! V6_PDRIVE bit 0	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! FFI1_SRVAL bit 0	ILOGIC[0]: ! FFI_LATCH	-	-	-	-	OLOGIC[0]: invert CLKDIV	OLOGIC[0]: ! CLK1_INV	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 2	-	-	OLOGIC[0]: FFO_RANK2_INIT bit 1	-	-	-	IOB[0]: V5_LVDS bit 8	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: FFI_SR_SYNC	ILOGIC[0]: SERDES	-	-	-	-	OLOGIC[0]: FFO_SR_ENABLE	OLOGIC[0]: DATA_WIDTH bit 4	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 1	-	OLOGIC[0]: INIT_DLY_CNT bit 6	-	-	IOB[0]: ! DCIUPDATEMODE_ASREQUIRED	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DDR_CLK_EDGE bit 1	ILOGIC[0]: ! FFI2_SRVAL bit 0	-	-	-	-	OLOGIC[0]: DATA_WIDTH bit 7	OLOGIC[0]: DATA_WIDTH bit 0	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 6	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[1] bit 7	OLOGIC[0]: FFO_RANK2_INIT bit 2	IODELAY[0]: ENABLE	-	-	-	-	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! FFI1_INIT bit 0	-	-	-	-	-	OLOGIC[0]: DATA_WIDTH bit 2	OLOGIC[0]: DATA_WIDTH bit 6	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 4	-	OLOGIC[0]: FFO_RANK2_INIT bit 3	-	IODELAY[0]: DELAY_TYPE bit 4	-	IOB[0]: ! V6_PDRIVE bit 1	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK3 bit 4	-	-	-	-	OLOGIC[0]: DATA_WIDTH bit 5	OLOGIC[0]: DATA_WIDTH bit 3	-	-	-	-	IODELAY[0]: ! IDELAY_VALUE_CUR bit 3	-	-	IOB[0]: OUTPUT_DELAY	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK2 bit 4	-	-	-	-	-	OLOGIC[0]: !invert T1	OLOGIC[0]: DATA_WIDTH bit 1	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 10	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 7	OLOGIC[0]: FFT_SR_ENABLE	OLOGIC[0]: INIT_FIFO_RESET bit 4	IODELAY[0]: DELAY_SRC bit 1	-	IOB[0]: V5_LVDS bit 7	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INIT_BITSLIP bit 4	-	-	-	-	OLOGIC[0]: !invert T3	OLOGIC[0]: !invert T2	-	-	-	OLOGIC[0]: TRISTATE_WIDTH bit 0	IODELAY[0]: DELAY_SRC bit 0	-	-	IOB[0]: ! V6_NDRIVE bit 1	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INIT_BITSLIP bit 3	-	-	-	-	-	OLOGIC[0]: FFT_RANK1_INIT bit 0	OLOGIC[0]: !invert T4	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 3	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 5	OLOGIC[0]: FFT_SR_SYNC	-	-	-	IOB[0]: PULL bit 2	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! FFI2_INIT bit 0	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 1	OLOGIC[0]: INIT_DLY_CNT bit 7	-	-	-	-	IOB[0]: PULL bit 1	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK3 bit 3	-	-	-	-	-	OLOGIC[0]: CLOCK_RATIO bit 0	-	-	-	OLOGIC[0]: ! FFT_SRVAL bit 2	OLOGIC[0]: INIT_FIFO_ADDR bit 4	-	-	IOB[0]: PULL bit 0	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! FFI3_INIT bit 0	-	-	-	-	-	OLOGIC[0]: CLOCK_RATIO bit 1	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 9	-	OLOGIC[0]: INIT_FIFO_RESET bit 12	IODELAY[0]: HIGH_PERFORMANCE_MODE	-	-	-	IOB[0]: ! V6_PDRIVE bit 2	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK2 bit 3	-	-	-	-	-	OLOGIC[0]: CLOCK_RATIO bit 2	OLOGIC[0]: CLOCK_RATIO bit 3	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 8	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKPERF bit 0	OLOGIC[0]: ! FFT_SRVAL bit 0	IODELAY[0]: DELAY_SRC bit 2	-	IOB[0]: V6_NSLEW bit 0	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INIT_BITSLIP bit 2	-	-	-	-	OLOGIC[0]: FFO_SR_SYNC	OLOGIC[0]: SELFHEAL	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 0	-	OLOGIC[0]: ! FFT_SRVAL bit 1	IODELAY[0]: ! IDELAY_VALUE_CUR bit 2	-	-	IOB[0]: V6_NSLEW bit 4	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK3 bit 2	-	-	-	-	-	-	OLOGIC[0]: FFT_RANK1_INIT bit 1	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[1] bit 2	-	OLOGIC[0]: INIT_DLY_CNT bit 9	-	IODELAY[0]: DELAY_SRC bit 4	-	IOB[0]: ! V6_NDRIVE bit 2	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! FFI3_SRVAL bit 0	ILOGIC[0]: ! FFI4_INIT bit 0	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 1	-	OLOGIC[0]: INIT_FIFO_ADDR bit 5	-	IODELAY[0]: DELAY_SRC bit 3	-	-	IOB[0]: V6_PDRIVE bit 3	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! FFI4_SRVAL bit 0	ILOGIC[0]: DDR_CLK_EDGE bit 0	-	-	-	-	OLOGIC[0]: ! FFO_SRVAL bit 0	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 5	OLOGIC[0]: ODELAY_USED	-	-	-	-	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK2 bit 2	-	-	-	-	OLOGIC[0]: ! FFO_INIT bit 0	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 10	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 7	OLOGIC[0]: ! FFT_INIT bit 0	OLOGIC[0]: INIT_FIFO_ADDR bit 6	-	-	-	IOB[0]: V6_PSLEW bit 0	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK3 bit 1	-	-	-	-	-	OLOGIC[0]: ! FFO_SRVAL bit 2	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 6	-	OLOGIC[0]: FFO_RANK2_SR_SYNC	-	-	-	IOB[0]: V5_LVDS bit 6	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK2 bit 1	-	-	-	-	-	OLOGIC[0]: FFT_RANK1_INIT bit 2	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 3	-	-	-	IODELAY[0]: !invert DATAIN	-	-	IOB[0]: PULL_DYNAMIC	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INIT_BITSLIP bit 1	-	-	-	-	-	-	OLOGIC[0]: ! FFO_SRVAL bit 1	-	-	-	-	-	-	IOB[0]: OUTPUT_PSEUDO_DIFF	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 4	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 0	-	-	IODELAY[0]: ! IDELAY_VALUE_CUR bit 1	-	-	IOB[0]: V6_OUTPUT_MISC bit 0	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DATA_RATE bit 0	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 9	-	-	OLOGIC[0]: INIT_PIPE_DATA1 bit 0	-	-	IOB[0]: ! V6_NDRIVE bit 3	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: I_DELAY_ENABLE	-	-	-	-	OLOGIC[0]: FFT_RANK1_INIT bit 3	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 8	-	OLOGIC[0]: INIT_FIFO_RESET bit 7	-	-	-	IOB[0]: V5_LVDS bit 5	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: D_EMU	-	-	-	-	-	OLOGIC[0]: FFT_RANK1_SR_SYNC	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 4	-	-	OLOGIC[0]: SERDES_MODE bit 0	-	-	IOB[0]: V6_NSLEW bit 2	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: SERDES_MODE bit 0	ILOGIC[0]: BITSLIP_SR_SYNC	-	-	-	-	-	OLOGIC[0]: SERDES	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[1] bit 2	-	-	OLOGIC[0]: INIT_DLY_CNT bit 2	-	-	-	IOB[0]: V6_PSLEW bit 1	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK3 bit 0	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 0	-	-	-	-	IOB[0]: V6_NSLEW bit 1	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK2 bit 0	-	-	-	-	OLOGIC[0]: INIT_LOADCNT bit 3	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 0	-	-	-	-	IOB[0]: OUTPUT_ENABLE bit 1	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INIT_BITSLIP bit 0	-	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 6	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 7	-	-	OLOGIC[0]: INIT_FIFO_RESET bit 10	-	-	IOB[0]: OUTPUT_ENABLE bit 0	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 3	-	-	-	-	OLOGIC[0]: FFO_RANK1_INIT bit 0	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 3	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 4	-	-	IODELAY[0]: ! IDELAY_VALUE_CUR bit 0	-	-	IOB[0]: V6_PSLEW bit 2	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 2	-	-	-	-	-	-	OLOGIC[0]: V5_MUX_O bit 1	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 1	OLOGIC[0]: INIT_PIPE_DATA1 bit 1	IODELAY[0]: DELAY_TYPE bit 0	-	IOB[0]: ! V6_PDRIVE bit 4	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_BITSLIPCNT bit 0	-	-	-	-	OLOGIC[0]: V5_MUX_O bit 2	OLOGIC[0]: INIT_PIPE_DATA1 bit 6	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 8	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 6	OLOGIC[0]: INIT_DLY_CNT bit 0	-	IODELAY[0]: ! IDATAIN_INV	-	-	IOB[0]: V6_OUTPUT_MISC bit 2	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: invert CLKDIV	ILOGIC[0]: ! CLK_INV bit 2	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA1 bit 7	OLOGIC[0]: invert D1	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 2	-	-	-	-	-	IOB[0]: V6_OUTPUT_MISC bit 1	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DATA_WIDTH bit 3	ILOGIC[0]: DYN_CLK_INV_EN	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 7	OLOGIC[0]: INIT_LOADCNT bit 2	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 5	SPEC_INT: mux CELL[0].IMUX_IOI_OCLKDIV[0] bit 1	OLOGIC[0]: DDR3_BYPASS	OLOGIC[0]: DDR3_DATA	-	-	-	IOB[0]: V5_LVDS bit 4	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! CLK_INV bit 1	-	-	-	-	OLOGIC[0]: FFO_RANK1_INIT bit 1	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 6	-	OLOGIC[0]: INIT_FIFO_RESET bit 5	OLOGIC[0]: !invert CLKPERF	IODELAY[0]: invert C	-	IOB[0]: V5_LVDS bit 3	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DATA_WIDTH bit 2	ILOGIC[0]: BITSLIP_ENABLE	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 0	-	OLOGIC[0]: INIT_FIFO_RESET bit 3	OLOGIC[0]: WC_DELAY	IODELAY[0]: CINVCTRL_SEL	-	-	IOB[0]: V6_NDRIVE bit 4	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_BITSLIPCNT bit 1	-	-	-	-	-	OLOGIC[0]: invert D2	OLOGIC[0]: INIT_PIPE_DATA1 bit 8	-	-	-	OLOGIC[0]: INIT_FIFO_ADDR bit 0	IODELAY[0]: IDELAY_VALUE_INIT bit 0	-	IOB[0]: V6_PSLEW bit 3	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_BITSLIPCNT bit 2	-	-	-	-	OLOGIC[0]: INIT_LOADCNT bit 1	OLOGIC[0]: FFO_LOADGEN_SR_SYNC	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 10	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 7	OLOGIC[0]: INIT_DLY_CNT bit 4	OLOGIC[0]: INIT_PIPE_DATA1 bit 2	IODELAY[0]: IDELAY_VALUE_INIT bit 1	-	-	IOB[0]: DCI_MODE bit 2	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DATA_WIDTH bit 1	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 5	-	OLOGIC[0]: INIT_FIFO_ADDR bit 3	-	IODELAY[0]: IDELAY_VALUE_INIT bit 2	-	IOB[0]: V5_LVDS bit 2	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DATA_WIDTH bit 0	ILOGIC[0]: ! CLK_INV bit 0	-	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 8	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 3	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 2	IODELAY[0]: IDELAY_VALUE_INIT bit 3	-	-	IOB[0]: V6_NSLEW bit 3	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INTERFACE_TYPE bit 2	ILOGIC[0]: ! OCLK1_INV	-	-	-	-	-	OLOGIC[0]: FFO_RANK1_INIT bit 2	-	-	OLOGIC[0]: INIT_FIFO_RESET bit 0	-	IODELAY[0]: IDELAY_VALUE_INIT bit 4	-	-	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INTERFACE_TYPE bit 0	-	-	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 10	-	-	OLOGIC[0]: INIT_PIPE_DATA1 bit 4	-	IODELAY[0]: DELAY_TYPE bit 1	-	-	-	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DYN_OCLK_INV_EN bit 1	-	-	-	-	OLOGIC[0]: invert D3	OLOGIC[0]: INIT_PIPE_DATA1 bit 10	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 2	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 4	-	OLOGIC[0]: INIT_FIFO_ADDR bit 1	IODELAY[0]: ALT_DELAY_VALUE bit 0	-	IOB[0]: DCI_MODE bit 0	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: DYN_OCLK_INV_EN bit 0	ILOGIC[0]: ! OCLK2_INV	-	-	-	-	OLOGIC[0]: INIT_LOADCNT bit 0	OLOGIC[0]: INIT_PIPE_DATA1 bit 9	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 8	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 9	-	OLOGIC[0]: INIT_DLY_CNT bit 5	IODELAY[0]: ALT_DELAY_VALUE bit 1	-	-	IOB[0]: VR	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_BITSLIPCNT bit 3	-	-	-	-	-	-	-	-	-	OLOGIC[0]: INIT_FIFO_ADDR bit 2	OLOGIC[0]: INIT_PIPE_DATA1 bit 3	IODELAY[0]: ALT_DELAY_VALUE bit 2	-	IOB[0]: DCI_MODE bit 1	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]: invert D4	SPEC_INT: mux CELL[0].IMUX_IOI_OCLK[0] bit 1	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 4	-	IODELAY[0]: ALT_DELAY_VALUE bit 3	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: INTERFACE_TYPE bit 1	-	-	-	-	-	OLOGIC[0]: FFO_RANK1_INIT bit 3	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 1	-	OLOGIC[0]: INIT_FIFO_RESET bit 6	IODELAY[0]: ALT_DELAY_VALUE bit 4	-	IOB[0]: V6_PSLEW bit 4	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: MUX_TSBYPASS bit 0	ILOGIC[0]: DYN_CLKDIV_INV_EN	-	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA1 bit 11	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 4	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 6	-	OLOGIC[0]: INIT_FIFO_RESET bit 1	IODELAY[0]: DELAY_TYPE bit 3	-	-	IOB[0]: V6_OUTPUT_MISC bit 3	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: I_TSBYPASS_ENABLE	OLOGIC[0]: MISR_CLK_SELECT bit 1	-	-	-	-	OLOGIC[0]: invert D5	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 10	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 7	OLOGIC[0]: INIT_FIFO_ADDR bit 7	OLOGIC[0]: INIT_PIPE_DATA1 bit 5	IODELAY[0]: DELAY_TYPE bit 2	-	IOB[0]: V5_LVDS bit 1	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: FFI_TSBYPASS_ENABLE	OLOGIC[0]: MISR_CLK_SELECT bit 0	-	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 0	OLOGIC[0]: INIT_FIFO_ADDR bit 9	-	-	-	-	IOB[0]: V6_PDRIVE bit 5	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 1	-	-	-	-	-	-	OLOGIC[0]: FFO_RANK1_INIT bit 4	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 3	-	OLOGIC[0]: INTERFACE_TYPE bit 0	-	-	-	IOB[0]: V6_NDRIVE bit 5	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! INIT_RANK1_PARTIAL bit 0	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 9	OLOGIC[0]: invert D6	-	-	OLOGIC[0]: INIT_FIFO_RESET bit 9	-	-	-	-	IOB[0]: V5_LVDS bit 0	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: FFI_DELAY_ENABLE	OLOGIC[0]: MISR_ENABLE	-	-	-	-	-	-	-	-	OLOGIC[0]: INIT_FIFO_RESET bit 2	-	-	-	IOB[0]: IBUF_DIFF_HP	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]: MISR_ENABLE_FDBK	-	-	-	-	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 9	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 3	-	-	-	IOB[0]: VREF_SYSMON	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]: INIT_PIPE_DATA0 bit 11	-	-	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 8	-	OLOGIC[0]: INIT_FIFO_ADDR bit 8	-	-	IOB[0]: IBUF_VREF_HP	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[0]: FFO_RANK1_INIT bit 5	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 5	-	OLOGIC[0]: INIT_DLY_CNT bit 8	OLOGIC[0]: INIT_PIPE_DATA0 bit 5	-	-	-	IOB[0]: IBUF_MODE bit 1	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[0]: ! D_INV	OLOGIC[0]: MISR_RESET	-	-	-	-	-	OLOGIC[0]: FFO_RANK1_SR_SYNC	SPEC_INT: mux CELL[0].IMUX_IOI_ICLK[0] bit 2	-	OLOGIC[0]: INIT_FIFO_ADDR bit 10	-	-	-	IOB[0]: IBUF_MODE bit 0	-	-	-

virtex6 IO rect MAIN[1]
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43
B63	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: MISR_RESET	ILOGIC[1]: ! D_INV	-	-	-	-	OLOGIC[1]: FFO_RANK1_SR_SYNC	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 0	-	OLOGIC[1]: INIT_FIFO_ADDR bit 10	-	-	-	IOB[1]: IBUF_MODE bit 0	-	-
B62	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: FFO_RANK1_INIT bit 5	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 3	OLOGIC[1]: INIT_PIPE_DATA0 bit 5	OLOGIC[1]: INIT_DLY_CNT bit 8	-	-	IOB[1]: IBUF_MODE bit 1	-	-	-
B61	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA0 bit 11	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 7	-	OLOGIC[1]: INIT_FIFO_ADDR bit 8	-	-	-	-	IOB[1]: IBUF_VREF_HP	-	-
B60	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: MISR_ENABLE_FDBK	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 8	OLOGIC[1]: INIT_PIPE_DATA0 bit 3	-	-	-	IOB[1]: VREF_SYSMON	-	-	-
B59	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: MISR_ENABLE	ILOGIC[1]: FFI_DELAY_ENABLE	-	-	-	-	-	-	-	-	-	OLOGIC[1]: INIT_FIFO_RESET bit 2	-	-	-	IOB[1]: IBUF_DIFF_HP	-	-
B58	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 0	-	-	-	-	-	OLOGIC[1]: invert D6	OLOGIC[1]: INIT_PIPE_DATA0 bit 9	-	-	-	OLOGIC[1]: INIT_FIFO_RESET bit 9	-	-	IOB[1]: V5_LVDS bit 0	-	-	-
B57	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 1	-	-	-	-	OLOGIC[1]: FFO_RANK1_INIT bit 4	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 1	-	OLOGIC[1]: INTERFACE_TYPE bit 0	-	-	-	IOB[1]: V6_NDRIVE bit 5	-	-
B56	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: MISR_CLK_SELECT bit 0	ILOGIC[1]: FFI_TSBYPASS_ENABLE	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 5	-	-	OLOGIC[1]: INIT_FIFO_ADDR bit 9	-	-	IOB[1]: V6_PDRIVE bit 5	-	-	-
B55	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: MISR_CLK_SELECT bit 1	ILOGIC[1]: I_TSBYPASS_ENABLE	-	-	-	-	-	OLOGIC[1]: invert D5	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 10	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 9	OLOGIC[1]: INIT_PIPE_DATA1 bit 5	OLOGIC[1]: INIT_FIFO_ADDR bit 7	-	IODELAY[1]: DELAY_TYPE bit 2	-	IOB[1]: V5_LVDS bit 1	-	-
B54	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: DYN_CLKDIV_INV_EN	ILOGIC[1]: MUX_TSBYPASS bit 0	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 11	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 4	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 2	OLOGIC[1]: INIT_FIFO_RESET bit 1	-	-	IODELAY[1]: DELAY_TYPE bit 4	IOB[1]: V6_OUTPUT_MISC bit 3	-	-	-
B53	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INTERFACE_TYPE bit 1	-	-	-	-	-	OLOGIC[1]: FFO_RANK1_INIT bit 3	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[0] bit 6	-	OLOGIC[1]: INIT_FIFO_RESET bit 6	-	-	IODELAY[1]: ALT_DELAY_VALUE bit 4	-	IOB[1]: V6_PSLEW bit 4	-	-
B52	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	OLOGIC[1]: invert D4	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 0	-	OLOGIC[1]: INIT_PIPE_DATA0 bit 4	-	IODELAY[1]: ALT_DELAY_VALUE bit 3	-	-	-	-
B51	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_BITSLIPCNT bit 3	-	-	-	-	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 3	OLOGIC[1]: INIT_FIFO_ADDR bit 2	-	IODELAY[1]: ALT_DELAY_VALUE bit 2	-	IOB[1]: DCI_MODE bit 1	-	-
B50	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! OCLK2_INV	ILOGIC[1]: DYN_OCLK_INV_EN bit 1	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 9	OLOGIC[1]: INIT_LOADCNT bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 8	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 7	OLOGIC[1]: INIT_DLY_CNT bit 5	-	-	IODELAY[1]: ALT_DELAY_VALUE bit 1	IOB[1]: VR	-	-	-
B49	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: DYN_OCLK_INV_EN bit 0	-	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 10	OLOGIC[1]: invert D3	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 3	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 1	OLOGIC[1]: INIT_FIFO_ADDR bit 1	-	-	IODELAY[1]: ALT_DELAY_VALUE bit 0	-	IOB[1]: DCI_MODE bit 0	-	-
B48	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INTERFACE_TYPE bit 0	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA0 bit 10	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 4	-	IODELAY[1]: DELAY_TYPE bit 1	-	-	-	-
B47	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! OCLK1_INV	ILOGIC[1]: INTERFACE_TYPE bit 2	-	-	-	-	OLOGIC[1]: FFO_RANK1_INIT bit 2	-	-	-	-	OLOGIC[1]: INIT_FIFO_RESET bit 0	-	IODELAY[1]: IDELAY_VALUE_INIT bit 4	-	-	-	-
B46	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! CLK_INV bit 2	ILOGIC[1]: DATA_WIDTH bit 0	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA0 bit 8	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 2	OLOGIC[1]: INIT_PIPE_DATA0 bit 2	-	-	IODELAY[1]: IDELAY_VALUE_INIT bit 3	IOB[1]: V6_NSLEW bit 3	-	-	-
B45	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: DATA_WIDTH bit 1	-	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 4	-	OLOGIC[1]: INIT_FIFO_ADDR bit 3	-	IODELAY[1]: IDELAY_VALUE_INIT bit 2	-	IOB[1]: V5_LVDS bit 2	-	-
B44	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_BITSLIPCNT bit 2	-	-	-	-	-	OLOGIC[1]: FFO_LOADGEN_SR_SYNC	OLOGIC[1]: INIT_LOADCNT bit 1	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 10	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 9	OLOGIC[1]: INIT_PIPE_DATA1 bit 2	OLOGIC[1]: INIT_DLY_CNT bit 4	-	IODELAY[1]: IDELAY_VALUE_INIT bit 1	IOB[1]: DCI_MODE bit 2	-	-	-
B43	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_BITSLIPCNT bit 1	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 8	OLOGIC[1]: invert D2	-	-	OLOGIC[1]: INIT_FIFO_ADDR bit 0	-	-	IODELAY[1]: IDELAY_VALUE_INIT bit 0	-	IOB[1]: V6_PSLEW bit 3	-	-
B42	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: BITSLIP_ENABLE	ILOGIC[1]: DATA_WIDTH bit 2	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 5	OLOGIC[1]: WC_DELAY	OLOGIC[1]: INIT_FIFO_RESET bit 3	-	IODELAY[1]: CINVCTRL_SEL	IOB[1]: V6_NDRIVE bit 4	-	-	-
B41	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! CLK_INV bit 1	-	-	-	-	-	-	OLOGIC[1]: FFO_RANK1_INIT bit 1	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[0] bit 6	OLOGIC[1]: !invert CLKPERF	OLOGIC[1]: INIT_FIFO_RESET bit 5	-	IODELAY[1]: invert C	-	IOB[1]: V5_LVDS bit 3	-	-
B40	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: DYN_CLK_INV_EN	ILOGIC[1]: DATA_WIDTH bit 3	-	-	-	-	OLOGIC[1]: INIT_LOADCNT bit 2	OLOGIC[1]: INIT_PIPE_DATA0 bit 7	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 7	OLOGIC[1]: DDR3_DATA	OLOGIC[1]: DDR3_BYPASS	-	-	IOB[1]: V5_LVDS bit 4	-	-	-
B39	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! CLK_INV bit 0	ILOGIC[1]: invert CLKDIV	-	-	-	-	OLOGIC[1]: invert D1	OLOGIC[1]: INIT_PIPE_DATA1 bit 7	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 1	-	-	-	-	-	IOB[1]: V6_OUTPUT_MISC bit 1	-	-
B38	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_BITSLIPCNT bit 0	-	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 6	OLOGIC[1]: V5_MUX_O bit 2	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 5	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 8	-	OLOGIC[1]: INIT_DLY_CNT bit 0	-	IODELAY[1]: ! IDATAIN_INV	IOB[1]: V6_OUTPUT_MISC bit 2	-	-	-
B37	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 2	-	-	-	-	OLOGIC[1]: V5_MUX_O bit 1	-	-	-	OLOGIC[1]: INIT_PIPE_DATA1 bit 1	OLOGIC[1]: INIT_PIPE_DATA0 bit 1	-	IODELAY[1]: DELAY_TYPE bit 0	-	IOB[1]: ! V6_PDRIVE bit 4	-	-
B36	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 3	-	-	-	-	-	-	OLOGIC[1]: FFO_RANK1_INIT bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 3	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 2	-	-	-	IODELAY[1]: ! IDELAY_VALUE_CUR bit 0	IOB[1]: V6_PSLEW bit 2	-	-	-
B35	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INIT_BITSLIP bit 0	-	-	-	-	-	OLOGIC[1]: INIT_PIPE_DATA0 bit 6	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 6	OLOGIC[1]: INIT_FIFO_RESET bit 10	-	-	-	-	IOB[1]: OUTPUT_ENABLE bit 1	-	-
B34	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK2 bit 0	-	-	-	-	-	-	OLOGIC[1]: INIT_LOADCNT bit 3	-	-	-	OLOGIC[1]: INIT_PIPE_DATA0 bit 0	-	-	IOB[1]: OUTPUT_ENABLE bit 0	-	-	-
B33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK3 bit 0	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[0] bit 4	-	-	-	-	-	-	IOB[1]: V6_NSLEW bit 1	-	-
B32	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: BITSLIP_SR_SYNC	ILOGIC[1]: SERDES_MODE bit 0	-	-	-	-	OLOGIC[1]: SERDES	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 0	OLOGIC[1]: INIT_DLY_CNT bit 2	-	-	-	IOB[1]: V6_PSLEW bit 1	-	-	-
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: D_EMU	-	-	-	-	-	OLOGIC[1]: FFT_RANK1_SR_SYNC	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 2	OLOGIC[1]: SERDES_MODE bit 0	-	-	-	-	IOB[1]: V6_NSLEW bit 2	-	-
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: I_DELAY_ENABLE	-	-	-	-	-	-	OLOGIC[1]: FFT_RANK1_INIT bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 7	-	OLOGIC[1]: INIT_FIFO_RESET bit 7	-	-	-	IOB[1]: V5_LVDS bit 5	-	-	-
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: DATA_RATE bit 0	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 8	OLOGIC[1]: INIT_PIPE_DATA1 bit 0	-	-	-	-	IOB[1]: ! V6_NDRIVE bit 3	-	-
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK1_PARTIAL bit 4	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 5	-	-	-	-	IODELAY[1]: ! IDELAY_VALUE_CUR bit 1	IOB[1]: V6_OUTPUT_MISC bit 0	-	-	-
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INIT_BITSLIP bit 1	-	-	-	-	OLOGIC[1]: ! FFO_SRVAL bit 1	-	-	-	-	-	-	-	-	-	-	-
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK2 bit 1	-	-	-	-	-	OLOGIC[1]: FFT_RANK1_INIT bit 1	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 1	-	-	-	IODELAY[1]: !invert DATAIN	IOB[1]: PULL_DYNAMIC	-	-	-
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK3 bit 1	-	-	-	-	-	OLOGIC[1]: ! FFO_SRVAL bit 2	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 4	-	OLOGIC[1]: FFO_RANK2_SR_SYNC	-	-	-	IOB[1]: V5_LVDS bit 6	-	-
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK2 bit 2	-	-	-	-	-	-	OLOGIC[1]: ! FFO_INIT bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 10	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 9	OLOGIC[1]: INIT_FIFO_ADDR bit 6	OLOGIC[1]: ! FFT_INIT bit 0	-	-	IOB[1]: V6_PSLEW bit 0	-	-	-
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: DDR_CLK_EDGE bit 0	ILOGIC[1]: ! FFI4_SRVAL bit 0	-	-	-	-	-	OLOGIC[1]: ! FFO_SRVAL bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 3	-	-	OLOGIC[1]: ODELAY_USED	-	-	-	-	-	-
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! FFI4_INIT bit 0	ILOGIC[1]: ! FFI3_SRVAL bit 0	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_ICLK[1] bit 6	-	OLOGIC[1]: INIT_FIFO_ADDR bit 5	-	IODELAY[1]: DELAY_SRC bit 3	IOB[1]: V6_PDRIVE bit 3	-	-	-
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK3 bit 2	-	-	-	-	OLOGIC[1]: FFT_RANK1_INIT bit 2	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 1	-	OLOGIC[1]: INIT_DLY_CNT bit 9	-	IODELAY[1]: DELAY_SRC bit 4	-	IOB[1]: ! V6_NDRIVE bit 2	-	-
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INIT_BITSLIP bit 2	-	-	-	-	-	OLOGIC[1]: SELFHEAL	OLOGIC[1]: FFO_SR_SYNC	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 5	-	OLOGIC[1]: ! FFT_SRVAL bit 1	-	-	IODELAY[1]: ! IDELAY_VALUE_CUR bit 2	IOB[1]: V6_NSLEW bit 4	-	-	-
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK2 bit 3	-	-	-	-	OLOGIC[1]: CLOCK_RATIO bit 3	OLOGIC[1]: CLOCK_RATIO bit 2	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 7	-	OLOGIC[1]: ! FFT_SRVAL bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKPERF bit 0	-	IODELAY[1]: DELAY_SRC bit 2	-	IOB[1]: V6_NSLEW bit 0	-	-
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! FFI3_INIT bit 0	-	-	-	-	-	OLOGIC[1]: CLOCK_RATIO bit 1	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 8	IODELAY[1]: HIGH_PERFORMANCE_MODE	OLOGIC[1]: INIT_FIFO_RESET bit 12	-	-	IOB[1]: ! V6_PDRIVE bit 2	-	-	-
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK3 bit 3	-	-	-	-	-	OLOGIC[1]: CLOCK_RATIO bit 0	-	-	OLOGIC[1]: INIT_FIFO_ADDR bit 4	OLOGIC[1]: ! FFT_SRVAL bit 2	-	-	-	IOB[1]: PULL bit 0	-	-
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! FFI2_INIT bit 0	-	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 0	-	-	OLOGIC[1]: INIT_DLY_CNT bit 7	-	-	IOB[1]: PULL bit 1	-	-	-
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INIT_BITSLIP bit 3	-	-	-	-	OLOGIC[1]: !invert T4	OLOGIC[1]: FFT_RANK1_INIT bit 3	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 4	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 2	-	OLOGIC[1]: FFT_SR_SYNC	-	-	-	IOB[1]: PULL bit 2	-	-
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INIT_BITSLIP bit 4	-	-	-	-	-	OLOGIC[1]: !invert T2	OLOGIC[1]: !invert T3	-	-	OLOGIC[1]: TRISTATE_WIDTH bit 0	-	-	IODELAY[1]: DELAY_SRC bit 0	IOB[1]: ! V6_NDRIVE bit 1	-	-	-
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK2 bit 4	-	-	-	-	OLOGIC[1]: DATA_WIDTH bit 1	OLOGIC[1]: !invert T1	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 10	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 9	OLOGIC[1]: INIT_FIFO_RESET bit 4	OLOGIC[1]: FFT_SR_ENABLE	-	IODELAY[1]: DELAY_SRC bit 1	-	IOB[1]: V5_LVDS bit 7	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK3 bit 4	-	-	-	-	-	OLOGIC[1]: DATA_WIDTH bit 3	OLOGIC[1]: DATA_WIDTH bit 5	-	-	-	-	-	IODELAY[1]: ! IDELAY_VALUE_CUR bit 3	IOB[1]: OUTPUT_DELAY	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! FFI1_INIT bit 0	-	-	-	-	OLOGIC[1]: DATA_WIDTH bit 6	OLOGIC[1]: DATA_WIDTH bit 2	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 3	-	OLOGIC[1]: FFO_RANK2_INIT bit 3	-	IODELAY[1]: DELAY_TYPE bit 3	-	IOB[1]: ! V6_PDRIVE bit 1	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! FFI2_SRVAL bit 0	ILOGIC[1]: DDR_CLK_EDGE bit 1	-	-	-	-	OLOGIC[1]: DATA_WIDTH bit 0	OLOGIC[1]: DATA_WIDTH bit 7	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 6	SPEC_INT: mux CELL[1].IMUX_IOI_OCLK[1] bit 6	IODELAY[1]: ENABLE	OLOGIC[1]: FFO_RANK2_INIT bit 2	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: SERDES	ILOGIC[1]: FFI_SR_SYNC	-	-	-	-	OLOGIC[1]: DATA_WIDTH bit 4	OLOGIC[1]: FFO_SR_ENABLE	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 0	-	OLOGIC[1]: INIT_DLY_CNT bit 6	-	-	-	-	IOB[1]: ! DCIUPDATEMODE_ASREQUIRED	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! FFI_LATCH	ILOGIC[1]: ! FFI1_SRVAL bit 0	-	-	-	-	OLOGIC[1]: ! CLK1_INV	OLOGIC[1]: invert CLKDIV	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 1	OLOGIC[1]: FFO_RANK2_INIT bit 1	-	-	-	IOB[1]: V5_LVDS bit 8	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK3 bit 5	-	-	-	-	-	OLOGIC[1]: ! CLK2_INV	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 5	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 7	OLOGIC[1]: FFO_RANK2_INIT bit 0	OLOGIC[1]: INIT_FIFO_RESET bit 11	-	-	-	IOB[1]: ! V6_PDRIVE bit 0	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_RANK2 bit 5	-	-	-	-	-	OLOGIC[1]: V5_MUX_O bit 4	-	-	-	-	-	-	IODELAY[1]: ! IDELAY_VALUE_CUR bit 4	IOB[1]: DCI_MISC bit 1	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: INIT_BITSLIP bit 5	-	-	-	-	OLOGIC[1]: V5_MUX_O bit 3	OLOGIC[1]: V5_MUX_O bit 0	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 3	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 2	-	-	-	-	-	IOB[1]: DCI_MISC bit 0	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_CE bit 0	-	-	-	-	-	-	-	-	-	OLOGIC[1]: INIT_DLY_CNT bit 1	OLOGIC[1]: V5_MUX_T bit 1	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: ! INIT_CE bit 1	-	-	-	-	-	-	-	-	IODELAY[1]: EXTRA_DELAY	OLOGIC[1]: V5_MUX_T bit 2	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: FFI_REV_ENABLE	ILOGIC[1]: READBACK_I bit 0	-	-	-	-	-	-	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 4	SPEC_INT: mux CELL[1].IMUX_IOI_OCLKDIV[1] bit 8	OLOGIC[1]: V5_MUX_T bit 3	OLOGIC[1]: INIT_FIFO_RESET bit 8	-	-	IOB[1]: ! V6_NDRIVE bit 0	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: RANK23_DLY	ILOGIC[1]: NUM_CE bit 0	-	-	-	-	-	ILOGIC[1]: D_EMU_OPTION bit 2	-	-	-	OLOGIC[1]: V5_MUX_T bit 4	-	-	-	IOB[1]: DCI_T	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	ILOGIC[1]: FFI_SR_ENABLE	ILOGIC[1]: RANK12_DLY	-	-	-	-	ILOGIC[1]: D_EMU_OPTION bit 1	ILOGIC[1]: D_EMU_OPTION bit 0	-	-	OLOGIC[1]: INIT_DLY_CNT bit 3	OLOGIC[1]: V5_MUX_T bit 0	-	-	IOB[1]: IBUF_MODE bit 2	-	-	-

Tile HCLK_IO

Cells: 8

Switchbox HCLK_IO_INT

virtex6 HCLK_IO switchbox HCLK_IO_INT programmable buffers
Destination	Source	Bit
CELL[4].PERF_BUF[0]	CELL[4].PERF_ROW[0]	MAIN[36][23]
CELL[4].PERF_BUF[1]	CELL[4].PERF_ROW[1]	MAIN[37][15]
CELL[4].PERF_BUF[2]	CELL[4].PERF_ROW[2]	MAIN[36][14]
CELL[4].PERF_BUF[3]	CELL[4].PERF_ROW[3]	MAIN[37][14]
CELL[4].HCLK_IO[0]	CELL[4].HCLK_ROW[0]	MAIN[29][20]
CELL[4].HCLK_IO[1]	CELL[4].HCLK_ROW[1]	MAIN[29][21]
CELL[4].HCLK_IO[2]	CELL[4].HCLK_ROW[2]	MAIN[29][22]
CELL[4].HCLK_IO[3]	CELL[4].HCLK_ROW[3]	MAIN[29][23]
CELL[4].HCLK_IO[4]	CELL[4].HCLK_ROW[4]	MAIN[29][24]
CELL[4].HCLK_IO[5]	CELL[4].HCLK_ROW[5]	MAIN[29][25]
CELL[4].HCLK_IO[6]	CELL[4].HCLK_ROW[6]	MAIN[29][26]
CELL[4].HCLK_IO[7]	CELL[4].HCLK_ROW[7]	MAIN[29][27]
CELL[4].HCLK_IO[8]	CELL[4].HCLK_ROW[8]	MAIN[29][28]
CELL[4].HCLK_IO[9]	CELL[4].HCLK_ROW[9]	MAIN[29][29]
CELL[4].HCLK_IO[10]	CELL[4].HCLK_ROW[10]	MAIN[29][30]
CELL[4].HCLK_IO[11]	CELL[4].HCLK_ROW[11]	MAIN[29][31]
CELL[4].RCLK_IO[0]	CELL[4].RCLK_ROW[0]	MAIN[29][14]
CELL[4].RCLK_IO[1]	CELL[4].RCLK_ROW[1]	MAIN[29][15]
CELL[4].RCLK_IO[2]	CELL[4].RCLK_ROW[2]	MAIN[29][16]
CELL[4].RCLK_IO[3]	CELL[4].RCLK_ROW[3]	MAIN[29][17]
CELL[4].RCLK_IO[4]	CELL[4].RCLK_ROW[4]	MAIN[29][18]
CELL[4].RCLK_IO[5]	CELL[4].RCLK_ROW[5]	MAIN[29][19]
CELL[4].VIOCLK_S_BUF[0]	CELL[4].VIOCLK_S[0]	MAIN[37][24]
CELL[4].VIOCLK_S_BUF[1]	CELL[4].VIOCLK_S[1]	MAIN[37][31]
CELL[4].VIOCLK_N_BUF[0]	CELL[4].VIOCLK_N[0]	MAIN[37][16]
CELL[4].VIOCLK_N_BUF[1]	CELL[4].VIOCLK_N[1]	MAIN[37][23]
CELL[4].VOCLK[0]	CELL[4].PERF_BUF[0]	MAIN[39][28]
CELL[4].VOCLK[1]	CELL[4].PERF_BUF[3]	MAIN[39][29]

virtex6 HCLK_IO switchbox HCLK_IO_INT pass gates
Destination	Source	Bit
CELL[4].RCLK_ROW[0]	CELL[4].PULLUP	MAIN[28][26]
CELL[4].RCLK_ROW[1]	CELL[4].PULLUP	MAIN[28][27]
CELL[4].RCLK_ROW[2]	CELL[4].PULLUP	MAIN[28][28]
CELL[4].RCLK_ROW[3]	CELL[4].PULLUP	MAIN[28][29]
CELL[4].RCLK_ROW[4]	CELL[4].PULLUP	MAIN[28][30]
CELL[4].RCLK_ROW[5]	CELL[4].PULLUP	MAIN[28][31]

virtex6 HCLK_IO switchbox HCLK_IO_INT delays
Destination	Source	Bits
CELL[4].IOCLK[0]	CELL[4].VIOCLK[0]	MAIN[36][27]
CELL[4].IOCLK[1]	CELL[4].SIOCLK[0]	MAIN[36][29]
CELL[4].IOCLK[2]	CELL[4].SIOCLK[1]	MAIN[36][18]
CELL[4].IOCLK[3]	CELL[4].VIOCLK[1]	MAIN[36][20]
CELL[4].IOCLK[4]	CELL[4].VIOCLK_S_BUF[0]	MAIN[36][25]
CELL[4].IOCLK[5]	CELL[4].VIOCLK_S_BUF[1]	MAIN[36][31]
CELL[4].IOCLK[6]	CELL[4].VIOCLK_N_BUF[0]	MAIN[36][16]
CELL[4].IOCLK[7]	CELL[4].VIOCLK_N_BUF[1]	MAIN[36][22]
Delay step
0		0
1		1

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[0]
Bits				Destination
MAIN[32][16]	MAIN[32][14]	MAIN[32][15]	MAIN[28][20]	CELL[4].RCLK_ROW[0]
				Source
0	0	0	0	off
0	0	0	1	CELL[4].VRCLK_N[0]
0	0	1	1	CELL[4].VRCLK[0]
0	1	0	1	CELL[4].VRCLK_N[1]
0	1	1	1	CELL[4].VRCLK[1]
1	0	0	1	CELL[4].VRCLK_S[0]
1	1	0	1	CELL[4].VRCLK_S[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[1]
Bits				Destination
MAIN[32][19]	MAIN[32][17]	MAIN[32][18]	MAIN[28][21]	CELL[4].RCLK_ROW[1]
				Source
0	0	0	0	off
0	0	0	1	CELL[4].VRCLK_N[0]
0	0	1	1	CELL[4].VRCLK[0]
0	1	0	1	CELL[4].VRCLK_N[1]
0	1	1	1	CELL[4].VRCLK[1]
1	0	0	1	CELL[4].VRCLK_S[0]
1	1	0	1	CELL[4].VRCLK_S[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[2]
Bits				Destination
MAIN[32][22]	MAIN[32][20]	MAIN[32][21]	MAIN[28][22]	CELL[4].RCLK_ROW[2]
				Source
0	0	0	0	off
0	0	0	1	CELL[4].VRCLK_N[0]
0	0	1	1	CELL[4].VRCLK[0]
0	1	0	1	CELL[4].VRCLK_N[1]
0	1	1	1	CELL[4].VRCLK[1]
1	0	0	1	CELL[4].VRCLK_S[0]
1	1	0	1	CELL[4].VRCLK_S[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[3]
Bits				Destination
MAIN[32][25]	MAIN[32][23]	MAIN[32][24]	MAIN[28][23]	CELL[4].RCLK_ROW[3]
				Source
0	0	0	0	off
0	0	0	1	CELL[4].VRCLK_N[0]
0	0	1	1	CELL[4].VRCLK[0]
0	1	0	1	CELL[4].VRCLK_N[1]
0	1	1	1	CELL[4].VRCLK[1]
1	0	0	1	CELL[4].VRCLK_S[0]
1	1	0	1	CELL[4].VRCLK_S[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[4]
Bits				Destination
MAIN[32][28]	MAIN[32][26]	MAIN[32][27]	MAIN[28][24]	CELL[4].RCLK_ROW[4]
				Source
0	0	0	0	off
0	0	0	1	CELL[4].VRCLK_N[0]
0	0	1	1	CELL[4].VRCLK[0]
0	1	0	1	CELL[4].VRCLK_N[1]
0	1	1	1	CELL[4].VRCLK[1]
1	0	0	1	CELL[4].VRCLK_S[0]
1	1	0	1	CELL[4].VRCLK_S[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes RCLK_ROW[5]
Bits				Destination
MAIN[32][31]	MAIN[32][29]	MAIN[32][30]	MAIN[28][25]	CELL[4].RCLK_ROW[5]
				Source
0	0	0	0	off
0	0	0	1	CELL[4].VRCLK_N[0]
0	0	1	1	CELL[4].VRCLK[0]
0	1	0	1	CELL[4].VRCLK_N[1]
0	1	1	1	CELL[4].VRCLK[1]
1	0	0	1	CELL[4].VRCLK_S[0]
1	1	0	1	CELL[4].VRCLK_S[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_IDELAYCTRL_REFCLK
Bits												Destination
MAIN[27][20]	MAIN[27][21]	MAIN[27][22]	MAIN[27][23]	MAIN[27][24]	MAIN[27][25]	MAIN[27][26]	MAIN[27][27]	MAIN[27][28]	MAIN[27][29]	MAIN[27][30]	MAIN[27][31]	CELL[4].IMUX_IDELAYCTRL_REFCLK
												Source
0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	1	CELL[4].HCLK_IO[0]
0	0	0	0	0	0	0	0	0	0	1	0	CELL[4].HCLK_IO[1]
0	0	0	0	0	0	0	0	0	1	0	0	CELL[4].HCLK_IO[2]
0	0	0	0	0	0	0	0	1	0	0	0	CELL[4].HCLK_IO[3]
0	0	0	0	0	0	0	1	0	0	0	0	CELL[4].HCLK_IO[4]
0	0	0	0	0	0	1	0	0	0	0	0	CELL[4].HCLK_IO[5]
0	0	0	0	0	1	0	0	0	0	0	0	CELL[4].HCLK_IO[6]
0	0	0	0	1	0	0	0	0	0	0	0	CELL[4].HCLK_IO[7]
0	0	0	1	0	0	0	0	0	0	0	0	CELL[4].HCLK_IO[8]
0	0	1	0	0	0	0	0	0	0	0	0	CELL[4].HCLK_IO[9]
0	1	0	0	0	0	0	0	0	0	0	0	CELL[4].HCLK_IO[10]
1	0	0	0	0	0	0	0	0	0	0	0	CELL[4].HCLK_IO[11]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFIO[0]
Bits	Destination
MAIN[37][28]	CELL[4].IMUX_BUFIO[0]
	Source
0	CELL[5].OUT_CLKPAD
1	CELL[4].PERF_BUF[1]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFIO[1]
Bits	Destination
MAIN[37][29]	CELL[4].IMUX_BUFIO[1]
	Source
0	CELL[7].OUT_CLKPAD
1	CELL[4].PERF_BUF[0]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFIO[2]
Bits	Destination
MAIN[37][20]	CELL[4].IMUX_BUFIO[2]
	Source
0	CELL[1].OUT_CLKPAD
1	CELL[4].PERF_BUF[3]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFIO[3]
Bits	Destination
MAIN[37][21]	CELL[4].IMUX_BUFIO[3]
	Source
0	CELL[3].OUT_CLKPAD
1	CELL[4].PERF_BUF[2]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFR[0]
Bits																Destination
MAIN[31][19]	MAIN[31][18]	MAIN[31][17]	MAIN[31][16]	MAIN[30][21]	MAIN[30][20]	MAIN[30][19]	MAIN[30][18]	MAIN[30][17]	MAIN[30][16]	MAIN[31][23]	MAIN[31][22]	MAIN[31][21]	MAIN[31][20]	MAIN[30][23]	MAIN[30][22]	CELL[4].IMUX_BUFR[0]
																Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[3].IMUX_IMUX[4]
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[4].IMUX_IMUX[4]
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[4].MGT_ROW[0]
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[4].MGT_ROW[1]
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[4].MGT_ROW[2]
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[4].MGT_ROW[3]
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	CELL[4].MGT_ROW[4]
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	CELL[4].MGT_ROW[5]
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[6]
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[7]
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[8]
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[9]
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[0]
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[1]
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[2]
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[3]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes IMUX_BUFR[1]
Bits																Destination
MAIN[31][27]	MAIN[31][26]	MAIN[31][25]	MAIN[31][24]	MAIN[30][29]	MAIN[30][28]	MAIN[30][27]	MAIN[30][26]	MAIN[30][25]	MAIN[30][24]	MAIN[31][31]	MAIN[31][30]	MAIN[31][29]	MAIN[31][28]	MAIN[30][31]	MAIN[30][30]	CELL[4].IMUX_BUFR[1]
																Source
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	off
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	CELL[3].IMUX_IMUX[4]
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	CELL[4].IMUX_IMUX[4]
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	CELL[4].MGT_ROW[0]
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	CELL[4].MGT_ROW[1]
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	CELL[4].MGT_ROW[2]
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	CELL[4].MGT_ROW[3]
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	CELL[4].MGT_ROW[4]
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	CELL[4].MGT_ROW[5]
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[6]
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[7]
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[8]
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	CELL[4].MGT_ROW[9]
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[0]
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[1]
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[2]
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	CELL[4].IMUX_BUFIO[3]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes OCLK[0]
Bits				Destination
MAIN[39][24]	MAIN[39][30]	MAIN[39][23]	MAIN[39][22]	CELL[4].OCLK[0]
				Source
0	0	0	0	CELL[4].VOCLK[0]
0	1	0	1	CELL[4].VOCLK_S[0]
1	0	1	0	CELL[4].VOCLK_N[0]

virtex6 HCLK_IO switchbox HCLK_IO_INT muxes OCLK[1]
Bits				Destination
MAIN[39][27]	MAIN[39][31]	MAIN[39][25]	MAIN[39][26]	CELL[4].OCLK[1]
				Source
0	0	0	0	CELL[4].VOCLK[1]
0	1	0	1	CELL[4].VOCLK_S[1]
1	0	1	0	CELL[4].VOCLK_N[1]

Bels BUFR

virtex6 HCLK_IO bel BUFR pins
Pin	Direction	BUFR[0]	BUFR[1]
I	in	CELL[4].IMUX_BUFR[0]	CELL[4].IMUX_BUFR[1]
CE	in	CELL[4].IMUX_IMUX[28]	CELL[3].IMUX_IMUX[9]
CLR	in	CELL[4].IMUX_IMUX[27]	CELL[3].IMUX_IMUX[29]
O	out	CELL[4].VRCLK[0]	CELL[4].VRCLK[1]

virtex6 HCLK_IO bel BUFR attribute bits
Attribute	BUFR[0]	BUFR[1]
ENABLE	MAIN[33][22]	MAIN[33][27]
DIVIDE	[enum: BUFR_DIVIDE]	[enum: BUFR_DIVIDE]

virtex6 HCLK_IO enum BUFR_DIVIDE
BUFR[0].DIVIDE	MAIN[33][20]	MAIN[33][19]	MAIN[33][18]	MAIN[33][21]
BUFR[1].DIVIDE	MAIN[33][30]	MAIN[33][29]	MAIN[33][28]	MAIN[33][31]
BYPASS	0	0	0	0
_1	0	0	0	1
_2	0	0	1	1
_3	0	1	0	1
_4	0	1	1	1
_5	1	0	0	1
_6	1	0	1	1
_7	1	1	0	1
_8	1	1	1	1

Bels BUFIO

virtex6 HCLK_IO bel BUFIO pins
Pin	Direction	BUFIO[0]	BUFIO[1]	BUFIO[2]	BUFIO[3]
I	in	CELL[4].IMUX_BUFIO[0]	CELL[4].IMUX_BUFIO[1]	CELL[4].IMUX_BUFIO[2]	CELL[4].IMUX_BUFIO[3]
DQSMASK	in	CELL[3].IMUX_IMUX[24]	CELL[3].IMUX_IMUX[23]	CELL[4].IMUX_IMUX[24]	CELL[4].IMUX_IMUX[23]
O	out	CELL[4].VIOCLK[0]	CELL[4].SIOCLK[0]	CELL[4].SIOCLK[1]	CELL[4].VIOCLK[1]

virtex6 HCLK_IO bel BUFIO attribute bits
Attribute	BUFIO[0]	BUFIO[1]	BUFIO[2]	BUFIO[3]
ENABLE	MAIN[37][25]	MAIN[37][30]	MAIN[37][17]	MAIN[37][22]
DQSMASK_ENABLE	MAIN[37][26]	MAIN[37][27]	MAIN[37][18]	MAIN[37][19]

Bels IDELAYCTRL

virtex6 HCLK_IO bel IDELAYCTRL pins
Pin	Direction	IDELAYCTRL
REFCLK	in	CELL[4].IMUX_IDELAYCTRL_REFCLK
RST	in	CELL[4].IMUX_IMUX[32]
RDY	out	CELL[4].OUT_BEL[6]
DNPULSEOUT	out	CELL[3].OUT_BEL[8]
UPPULSEOUT	out	CELL[3].OUT_BEL[11]
OUTN1	out	CELL[3].OUT_BEL[7]
OUTN65	out	CELL[3].OUT_BEL[6]

virtex6 HCLK_IO bel IDELAYCTRL attribute bits
Attribute	IDELAYCTRL
DLL_ENABLE	MAIN[38][30]
DELAY_ENABLE	MAIN[38][29]
VCTL_SEL bit 0	MAIN[38][27]
VCTL_SEL bit 1	MAIN[38][28]
RESET_STYLE	[enum: IDELAYCTRL_RESET_STYLE]
HIGH_PERFORMANCE_MODE	MAIN[38][22]
BIAS_MODE bit 0	MAIN[38][26]

virtex6 HCLK_IO enum IDELAYCTRL_RESET_STYLE
IDELAYCTRL.RESET_STYLE	MAIN[38][31]
V4	1
V5	0

Bels DCI

virtex6 HCLK_IO bel DCI pins
Pin	Direction	DCI
TSTCLK	in	CELL[3].IMUX_IMUX[27]
TSTRST	in	CELL[4].IMUX_IMUX[9]
TSTHLP	in	CELL[4].IMUX_IMUX[29]
TSTHLN	in	CELL[3].IMUX_IMUX[28]
INT_DCI_EN	in	CELL[3].IMUX_IMUX[26]
DCIDONE	out	CELL[4].OUT_BEL[11]

virtex6 HCLK_IO bel DCI attribute bits
Attribute	DCI
ENABLE	MAIN[42][31]
QUIET	MAIN[41][31]
V6_PMASK_TERM_VCC bit 0	MAIN[43][14]
V6_PMASK_TERM_VCC bit 1	MAIN[43][27]
V6_PMASK_TERM_VCC bit 2	MAIN[43][28]
V6_PMASK_TERM_VCC bit 3	MAIN[43][29]
V6_PMASK_TERM_VCC bit 4	MAIN[43][30]
V6_PMASK_TERM_VCC bit 5	MAIN[43][31]
V6_PMASK_TERM_SPLIT bit 0	MAIN[43][21]
V6_PMASK_TERM_SPLIT bit 1	MAIN[43][22]
V6_PMASK_TERM_SPLIT bit 2	MAIN[43][23]
V6_PMASK_TERM_SPLIT bit 3	MAIN[43][24]
V6_PMASK_TERM_SPLIT bit 4	MAIN[43][25]
V6_PMASK_TERM_SPLIT bit 5	MAIN[43][26]
V6_NMASK_TERM_SPLIT bit 0	MAIN[43][15]
V6_NMASK_TERM_SPLIT bit 1	MAIN[43][16]
V6_NMASK_TERM_SPLIT bit 2	MAIN[43][17]
V6_NMASK_TERM_SPLIT bit 3	MAIN[43][18]
V6_NMASK_TERM_SPLIT bit 4	MAIN[43][19]
V6_NMASK_TERM_SPLIT bit 5	MAIN[43][20]
TEST_ENABLE bit 0	MAIN[40][31]
TEST_ENABLE bit 1	MAIN[41][23]
CASCADE_FROM_ABOVE	MAIN[40][27]
CASCADE_FROM_BELOW	MAIN[40][28]
DYNAMIC_ENABLE	MAIN[42][29]
NREF_OUTPUT bit 0	MAIN[40][16]
NREF_OUTPUT bit 1	MAIN[40][17]
NREF_OUTPUT_HALF bit 0	MAIN[40][18]
NREF_OUTPUT_HALF bit 1	MAIN[40][19]
NREF_OUTPUT_HALF bit 2	MAIN[40][20]
NREF_TERM_SPLIT bit 0	MAIN[40][23]
NREF_TERM_SPLIT bit 1	MAIN[40][24]
NREF_TERM_SPLIT bit 2	MAIN[40][25]
PREF_OUTPUT bit 0	MAIN[41][14]
PREF_OUTPUT bit 1	MAIN[41][15]
PREF_OUTPUT_HALF bit 0	MAIN[41][16]
PREF_OUTPUT_HALF bit 1	MAIN[41][17]
PREF_OUTPUT_HALF bit 2	MAIN[41][18]
PREF_TERM_VCC bit 0	MAIN[40][14]
PREF_TERM_VCC bit 1	MAIN[40][15]
PREF_TERM_SPLIT bit 0	MAIN[41][19]
PREF_TERM_SPLIT bit 1	MAIN[41][20]
PREF_TERM_SPLIT bit 2	MAIN[41][21]

Bels BANK

virtex6 HCLK_IO bel BANK pins
Pin	Direction	BANK

virtex6 HCLK_IO bel BANK attribute bits
Attribute	BANK
V6_LVDSBIAS bit 0	MAIN[42][30]
V6_LVDSBIAS bit 1	MAIN[42][28]
V6_LVDSBIAS bit 2	MAIN[42][27]
V6_LVDSBIAS bit 3	MAIN[42][26]
V6_LVDSBIAS bit 4	MAIN[42][25]
V6_LVDSBIAS bit 5	MAIN[42][24]
V6_LVDSBIAS bit 6	MAIN[42][23]
V6_LVDSBIAS bit 7	MAIN[42][22]
V6_LVDSBIAS bit 8	MAIN[42][21]
V6_LVDSBIAS bit 9	MAIN[42][20]
V6_LVDSBIAS bit 10	MAIN[42][19]
V6_LVDSBIAS bit 11	MAIN[42][18]
V6_LVDSBIAS bit 12	MAIN[42][17]
V6_LVDSBIAS bit 13	MAIN[42][16]
V6_LVDSBIAS bit 14	MAIN[42][15]
V6_LVDSBIAS bit 15	MAIN[42][14]
V6_LVDSBIAS bit 16	MAIN[41][28]
INTERNAL_VREF	[enum: INTERNAL_VREF]

virtex6 HCLK_IO enum INTERNAL_VREF
BANK.INTERNAL_VREF	MAIN[40][30]	MAIN[40][29]	MAIN[41][29]	MAIN[41][24]	MAIN[41][30]	MAIN[40][26]
OFF	0	0	0	0	0	0
_600	0	0	0	0	1	1
_750	0	0	0	1	0	1
_900	0	0	1	0	0	1
_1100	0	1	0	0	0	1
_1250	1	0	0	0	0	1

Bel wires

virtex6 HCLK_IO bel wires
Wire	Pins
CELL[3].IMUX_IMUX[9]	BUFR[1].CE
CELL[3].IMUX_IMUX[23]	BUFIO[1].DQSMASK
CELL[3].IMUX_IMUX[24]	BUFIO[0].DQSMASK
CELL[3].IMUX_IMUX[26]	DCI.INT_DCI_EN
CELL[3].IMUX_IMUX[27]	DCI.TSTCLK
CELL[3].IMUX_IMUX[28]	DCI.TSTHLN
CELL[3].IMUX_IMUX[29]	BUFR[1].CLR
CELL[3].OUT_BEL[6]	IDELAYCTRL.OUTN65
CELL[3].OUT_BEL[7]	IDELAYCTRL.OUTN1
CELL[3].OUT_BEL[8]	IDELAYCTRL.DNPULSEOUT
CELL[3].OUT_BEL[11]	IDELAYCTRL.UPPULSEOUT
CELL[4].IMUX_IMUX[9]	DCI.TSTRST
CELL[4].IMUX_IMUX[23]	BUFIO[3].DQSMASK
CELL[4].IMUX_IMUX[24]	BUFIO[2].DQSMASK
CELL[4].IMUX_IMUX[27]	BUFR[0].CLR
CELL[4].IMUX_IMUX[28]	BUFR[0].CE
CELL[4].IMUX_IMUX[29]	DCI.TSTHLP
CELL[4].IMUX_IMUX[32]	IDELAYCTRL.RST
CELL[4].OUT_BEL[6]	IDELAYCTRL.RDY
CELL[4].OUT_BEL[11]	DCI.DCIDONE
CELL[4].IMUX_IDELAYCTRL_REFCLK	IDELAYCTRL.REFCLK
CELL[4].IMUX_BUFIO[0]	BUFIO[0].I
CELL[4].IMUX_BUFIO[1]	BUFIO[1].I
CELL[4].IMUX_BUFIO[2]	BUFIO[2].I
CELL[4].IMUX_BUFIO[3]	BUFIO[3].I
CELL[4].IMUX_BUFR[0]	BUFR[0].I
CELL[4].IMUX_BUFR[1]	BUFR[1].I
CELL[4].VRCLK[0]	BUFR[0].O
CELL[4].VRCLK[1]	BUFR[1].O
CELL[4].SIOCLK[0]	BUFIO[1].O
CELL[4].SIOCLK[1]	BUFIO[2].O
CELL[4].VIOCLK[0]	BUFIO[0].O
CELL[4].VIOCLK[1]	BUFIO[3].O

Bitstream

virtex6 HCLK_IO rect MAIN
Bit	Frame
Bit	F0	F1	F2	F3	F4	F5	F6	F7	F8	F9	F10	F11	F12	F13	F14	F15	F16	F17	F18	F19	F20	F21	F22	F23	F24	F25	F26	F27	F28	F29	F30	F31	F32	F33	F34	F35	F36	F37	F38	F39	F40	F41	F42	F43
B31	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 0	HCLK_IO_INT: pass CELL[4].RCLK_ROW[5] ← CELL[4].PULLUP	HCLK_IO_INT: buffer CELL[4].HCLK_IO[11] ← CELL[4].HCLK_ROW[11]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 1	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 5	HCLK_IO_INT: mux CELL[4].RCLK_ROW[5] bit 3	BUFR[1]: DIVIDE bit 0	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[5] ← CELL[4].VIOCLK_S_BUF[1] bit 0	HCLK_IO_INT: buffer CELL[4].VIOCLK_S_BUF[1] ← CELL[4].VIOCLK_S[1]	IDELAYCTRL: RESET_STYLE bit 0	HCLK_IO_INT: mux CELL[4].OCLK[1] bit 2	DCI: TEST_ENABLE bit 0	DCI: QUIET	DCI: ENABLE	DCI: V6_PMASK_TERM_VCC bit 5
B30	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 1	HCLK_IO_INT: pass CELL[4].RCLK_ROW[4] ← CELL[4].PULLUP	HCLK_IO_INT: buffer CELL[4].HCLK_IO[10] ← CELL[4].HCLK_ROW[10]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 0	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 4	HCLK_IO_INT: mux CELL[4].RCLK_ROW[5] bit 1	BUFR[1]: DIVIDE bit 3	-	-	-	BUFIO[1]: ENABLE	IDELAYCTRL: DLL_ENABLE	HCLK_IO_INT: mux CELL[4].OCLK[0] bit 2	BANK: INTERNAL_VREF bit 5	BANK: INTERNAL_VREF bit 1	BANK: V6_LVDSBIAS bit 0	DCI: V6_PMASK_TERM_VCC bit 4
B29	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 2	HCLK_IO_INT: pass CELL[4].RCLK_ROW[3] ← CELL[4].PULLUP	HCLK_IO_INT: buffer CELL[4].HCLK_IO[9] ← CELL[4].HCLK_ROW[9]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 11	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 3	HCLK_IO_INT: mux CELL[4].RCLK_ROW[5] bit 2	BUFR[1]: DIVIDE bit 2	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[1] ← CELL[4].SIOCLK[0] bit 0	HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[1] bit 0	IDELAYCTRL: DELAY_ENABLE	HCLK_IO_INT: buffer CELL[4].VOCLK[1] ← CELL[4].PERF_BUF[3]	BANK: INTERNAL_VREF bit 4	BANK: INTERNAL_VREF bit 3	DCI: DYNAMIC_ENABLE	DCI: V6_PMASK_TERM_VCC bit 3
B28	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 3	HCLK_IO_INT: pass CELL[4].RCLK_ROW[2] ← CELL[4].PULLUP	HCLK_IO_INT: buffer CELL[4].HCLK_IO[8] ← CELL[4].HCLK_ROW[8]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 10	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 2	HCLK_IO_INT: mux CELL[4].RCLK_ROW[4] bit 3	BUFR[1]: DIVIDE bit 1	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[0] bit 0	IDELAYCTRL: VCTL_SEL bit 1	HCLK_IO_INT: buffer CELL[4].VOCLK[0] ← CELL[4].PERF_BUF[0]	DCI: CASCADE_FROM_BELOW	BANK: V6_LVDSBIAS bit 16	BANK: V6_LVDSBIAS bit 1	DCI: V6_PMASK_TERM_VCC bit 2
B27	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 4	HCLK_IO_INT: pass CELL[4].RCLK_ROW[1] ← CELL[4].PULLUP	HCLK_IO_INT: buffer CELL[4].HCLK_IO[7] ← CELL[4].HCLK_ROW[7]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 9	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 15	HCLK_IO_INT: mux CELL[4].RCLK_ROW[4] bit 1	BUFR[1]: ENABLE	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[0] ← CELL[4].VIOCLK[0] bit 0	BUFIO[1]: DQSMASK_ENABLE	IDELAYCTRL: VCTL_SEL bit 0	HCLK_IO_INT: mux CELL[4].OCLK[1] bit 3	DCI: CASCADE_FROM_ABOVE	-	BANK: V6_LVDSBIAS bit 2	DCI: V6_PMASK_TERM_VCC bit 1
B26	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 5	HCLK_IO_INT: pass CELL[4].RCLK_ROW[0] ← CELL[4].PULLUP	HCLK_IO_INT: buffer CELL[4].HCLK_IO[6] ← CELL[4].HCLK_ROW[6]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 8	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 14	HCLK_IO_INT: mux CELL[4].RCLK_ROW[4] bit 2	-	-	-	-	BUFIO[0]: DQSMASK_ENABLE	IDELAYCTRL: BIAS_MODE bit 0	HCLK_IO_INT: mux CELL[4].OCLK[1] bit 0	BANK: INTERNAL_VREF bit 0	-	BANK: V6_LVDSBIAS bit 3	DCI: V6_PMASK_TERM_SPLIT bit 5
B25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 6	HCLK_IO_INT: mux CELL[4].RCLK_ROW[5] bit 0	HCLK_IO_INT: buffer CELL[4].HCLK_IO[5] ← CELL[4].HCLK_ROW[5]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 7	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 13	HCLK_IO_INT: mux CELL[4].RCLK_ROW[3] bit 3	-	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[4] ← CELL[4].VIOCLK_S_BUF[0] bit 0	BUFIO[0]: ENABLE	-	HCLK_IO_INT: mux CELL[4].OCLK[1] bit 1	DCI: NREF_TERM_SPLIT bit 2	-	BANK: V6_LVDSBIAS bit 4	DCI: V6_PMASK_TERM_SPLIT bit 4
B24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 7	HCLK_IO_INT: mux CELL[4].RCLK_ROW[4] bit 0	HCLK_IO_INT: buffer CELL[4].HCLK_IO[4] ← CELL[4].HCLK_ROW[4]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 6	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[1] bit 12	HCLK_IO_INT: mux CELL[4].RCLK_ROW[3] bit 1	-	-	-	-	HCLK_IO_INT: buffer CELL[4].VIOCLK_S_BUF[0] ← CELL[4].VIOCLK_S[0]	-	HCLK_IO_INT: mux CELL[4].OCLK[0] bit 3	DCI: NREF_TERM_SPLIT bit 1	BANK: INTERNAL_VREF bit 2	BANK: V6_LVDSBIAS bit 5	DCI: V6_PMASK_TERM_SPLIT bit 3
B23	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 8	HCLK_IO_INT: mux CELL[4].RCLK_ROW[3] bit 0	HCLK_IO_INT: buffer CELL[4].HCLK_IO[3] ← CELL[4].HCLK_ROW[3]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 1	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 5	HCLK_IO_INT: mux CELL[4].RCLK_ROW[3] bit 2	-	-	-	HCLK_IO_INT: buffer CELL[4].PERF_BUF[0] ← CELL[4].PERF_ROW[0]	HCLK_IO_INT: buffer CELL[4].VIOCLK_N_BUF[1] ← CELL[4].VIOCLK_N[1]	-	HCLK_IO_INT: mux CELL[4].OCLK[0] bit 1	DCI: NREF_TERM_SPLIT bit 0	DCI: TEST_ENABLE bit 1	BANK: V6_LVDSBIAS bit 6	DCI: V6_PMASK_TERM_SPLIT bit 2
B22	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 9	HCLK_IO_INT: mux CELL[4].RCLK_ROW[2] bit 0	HCLK_IO_INT: buffer CELL[4].HCLK_IO[2] ← CELL[4].HCLK_ROW[2]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 0	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 4	HCLK_IO_INT: mux CELL[4].RCLK_ROW[2] bit 3	BUFR[0]: ENABLE	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[7] ← CELL[4].VIOCLK_N_BUF[1] bit 0	BUFIO[3]: ENABLE	IDELAYCTRL: HIGH_PERFORMANCE_MODE	HCLK_IO_INT: mux CELL[4].OCLK[0] bit 0	-	-	BANK: V6_LVDSBIAS bit 7	DCI: V6_PMASK_TERM_SPLIT bit 1
B21	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 10	HCLK_IO_INT: mux CELL[4].RCLK_ROW[1] bit 0	HCLK_IO_INT: buffer CELL[4].HCLK_IO[1] ← CELL[4].HCLK_ROW[1]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 11	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 3	HCLK_IO_INT: mux CELL[4].RCLK_ROW[2] bit 1	BUFR[0]: DIVIDE bit 0	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[3] bit 0	-	-	-	DCI: PREF_TERM_SPLIT bit 2	BANK: V6_LVDSBIAS bit 8	DCI: V6_PMASK_TERM_SPLIT bit 0
B20	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: mux CELL[4].IMUX_IDELAYCTRL_REFCLK bit 11	HCLK_IO_INT: mux CELL[4].RCLK_ROW[0] bit 0	HCLK_IO_INT: buffer CELL[4].HCLK_IO[0] ← CELL[4].HCLK_ROW[0]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 10	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 2	HCLK_IO_INT: mux CELL[4].RCLK_ROW[2] bit 2	BUFR[0]: DIVIDE bit 3	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[3] ← CELL[4].VIOCLK[1] bit 0	HCLK_IO_INT: mux CELL[4].IMUX_BUFIO[2] bit 0	-	-	DCI: NREF_OUTPUT_HALF bit 2	DCI: PREF_TERM_SPLIT bit 1	BANK: V6_LVDSBIAS bit 9	DCI: V6_NMASK_TERM_SPLIT bit 5
B19	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[4].RCLK_IO[5] ← CELL[4].RCLK_ROW[5]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 9	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 15	HCLK_IO_INT: mux CELL[4].RCLK_ROW[1] bit 3	BUFR[0]: DIVIDE bit 2	-	-	-	BUFIO[3]: DQSMASK_ENABLE	-	-	DCI: NREF_OUTPUT_HALF bit 1	DCI: PREF_TERM_SPLIT bit 0	BANK: V6_LVDSBIAS bit 10	DCI: V6_NMASK_TERM_SPLIT bit 4
B18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[4].RCLK_IO[4] ← CELL[4].RCLK_ROW[4]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 8	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 14	HCLK_IO_INT: mux CELL[4].RCLK_ROW[1] bit 1	BUFR[0]: DIVIDE bit 1	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[2] ← CELL[4].SIOCLK[1] bit 0	BUFIO[2]: DQSMASK_ENABLE	-	-	DCI: NREF_OUTPUT_HALF bit 0	DCI: PREF_OUTPUT_HALF bit 2	BANK: V6_LVDSBIAS bit 11	DCI: V6_NMASK_TERM_SPLIT bit 3
B17	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[4].RCLK_IO[3] ← CELL[4].RCLK_ROW[3]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 7	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 13	HCLK_IO_INT: mux CELL[4].RCLK_ROW[1] bit 2	-	-	-	-	BUFIO[2]: ENABLE	-	-	DCI: NREF_OUTPUT bit 1	DCI: PREF_OUTPUT_HALF bit 1	BANK: V6_LVDSBIAS bit 12	DCI: V6_NMASK_TERM_SPLIT bit 2
B16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[4].RCLK_IO[2] ← CELL[4].RCLK_ROW[2]	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 6	HCLK_IO_INT: mux CELL[4].IMUX_BUFR[0] bit 12	HCLK_IO_INT: mux CELL[4].RCLK_ROW[0] bit 3	-	-	-	HCLK_IO_INT: delay CELL[4].IOCLK[6] ← CELL[4].VIOCLK_N_BUF[0] bit 0	HCLK_IO_INT: buffer CELL[4].VIOCLK_N_BUF[0] ← CELL[4].VIOCLK_N[0]	-	-	DCI: NREF_OUTPUT bit 0	DCI: PREF_OUTPUT_HALF bit 0	BANK: V6_LVDSBIAS bit 13	DCI: V6_NMASK_TERM_SPLIT bit 1
B15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[4].RCLK_IO[1] ← CELL[4].RCLK_ROW[1]	-	-	HCLK_IO_INT: mux CELL[4].RCLK_ROW[0] bit 1	-	-	-	-	HCLK_IO_INT: buffer CELL[4].PERF_BUF[1] ← CELL[4].PERF_ROW[1]	-	-	DCI: PREF_TERM_VCC bit 1	DCI: PREF_OUTPUT bit 1	BANK: V6_LVDSBIAS bit 14	DCI: V6_NMASK_TERM_SPLIT bit 0
B14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	HCLK_IO_INT: buffer CELL[4].RCLK_IO[0] ← CELL[4].RCLK_ROW[0]	-	-	HCLK_IO_INT: mux CELL[4].RCLK_ROW[0] bit 2	-	-	-	HCLK_IO_INT: buffer CELL[4].PERF_BUF[2] ← CELL[4].PERF_ROW[2]	HCLK_IO_INT: buffer CELL[4].PERF_BUF[3] ← CELL[4].PERF_ROW[3]	-	-	DCI: PREF_TERM_VCC bit 0	DCI: PREF_OUTPUT bit 0	BANK: V6_LVDSBIAS bit 15	DCI: V6_PMASK_TERM_VCC bit 0
B13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B10	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B9	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B5	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
B0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Tables

Device data iodelay-default

virtex6 device data iodelay-default
Device	IODELAY_V6_IDELAY_DEFAULT
xc6vlx760	0b11011
xc6vlx760l	0b11011
xc6vlx75t	0b10011
xc6vlx75tl	0b10011
xc6vcx75t	0b10011
xc6vlx130t	0b10110
xq6vlx130t	0b10110
xc6vlx130tl	0b10110
xq6vlx130tl	0b10110
xc6vcx130t	0b10110
xc6vlx195t	0b11011
xc6vlx195tl	0b11011
xc6vcx195t	0b11011
xc6vlx240t	0b11011
xq6vlx240t	0b11011
xc6vlx240tl	0b11011
xq6vlx240tl	0b11011
xc6vcx240t	0b11011
xc6vlx365t	0b01100
xc6vlx365tl	0b01100
xc6vlx550t	0b10110
xq6vlx550t	0b10110
xc6vlx550tl	0b10110
xq6vlx550tl	0b10110
xc6vsx315t	0b10010
xq6vsx315t	0b10010
xc6vsx315tl	0b10010
xq6vsx315tl	0b10010
xc6vsx475t	0b11000
xq6vsx475t	0b11000
xc6vsx475tl	0b11000
xq6vsx475tl	0b11000
xc6vhx250t	0b10010
xc6vhx255t	0b01100
xc6vhx380t	0b10010
xc6vhx565t	0b11000

Table IOB_DATA

virtex6 table IOB_DATA
Row	PDRIVE	NDRIVE	OUTPUT_MISC	PSLEW_FAST	NSLEW_FAST	PSLEW_SLOW	NSLEW_SLOW	PREF_OUTPUT	NREF_OUTPUT	PREF_OUTPUT_HALF	NREF_OUTPUT_HALF	PREF_TERM_VCC	PMASK_TERM_VCC	PREF_TERM_SPLIT	NREF_TERM_SPLIT	PMASK_TERM_SPLIT	NMASK_TERM_SPLIT
OFF	0b000000	0b000000	0b0000	0b00000	0b00000	-	-	0b00	0b00	0b000	0b000	0b00	0b000000	0b000	0b000	0b000000	0b000000
VREF	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
VR	0b000000	0b000000	-	0b11111	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS12_2	0b001111	0b000011	0b1000	0b11111	0b11000	0b00001	0b00001	-	-	-	-	-	-	-	-	-	-
LVCMOS12_4	0b011101	0b000110	0b1000	0b11111	0b11111	0b00001	0b00001	-	-	-	-	-	-	-	-	-	-
LVCMOS12_6	0b101010	0b001001	0b1000	0b11111	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS12_8	0b111001	0b001100	0b1000	0b11001	0b11111	0b00001	0b00011	-	-	-	-	-	-	-	-	-	-
LVCMOS15_2	0b001000	0b000011	0b1000	0b11111	0b00001	0b10010	0b00001	-	-	-	-	-	-	-	-	-	-
LVCMOS15_4	0b010000	0b000101	0b1000	0b11111	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS15_6	0b011000	0b000111	0b1000	0b11111	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS15_8	0b100000	0b001010	0b1000	0b01001	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS15_12	0b101111	0b001110	0b1000	0b01000	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS15_16	0b111111	0b010011	0b1000	0b00110	0b11111	0b00001	0b00111	-	-	-	-	-	-	-	-	-	-
LVCMOS18_2	0b000101	0b000010	0b0000	0b10001	0b11111	0b00001	0b00111	-	-	-	-	-	-	-	-	-	-
LVCMOS18_4	0b001010	0b000100	0b0000	0b11111	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS18_6	0b001111	0b000110	0b0000	0b00111	0b11111	0b00001	0b00101	-	-	-	-	-	-	-	-	-	-
LVCMOS18_8	0b010101	0b001000	0b0000	0b00110	0b11111	0b00001	0b00101	-	-	-	-	-	-	-	-	-	-
LVCMOS18_12	0b011111	0b001100	0b0000	0b00110	0b11111	0b00001	0b00100	-	-	-	-	-	-	-	-	-	-
LVCMOS18_16	0b100111	0b010000	0b0000	0b00110	0b11111	0b00001	0b00111	-	-	-	-	-	-	-	-	-	-
LVCMOS25_2	0b000100	0b000010	0b0000	0b11111	0b11111	0b00000	0b11111	-	-	-	-	-	-	-	-	-	-
LVCMOS25_4	0b001000	0b000100	0b0000	0b11111	0b11111	0b00000	0b11111	-	-	-	-	-	-	-	-	-	-
LVCMOS25_6	0b001100	0b000110	0b0000	0b00010	0b11111	0b00001	0b01010	-	-	-	-	-	-	-	-	-	-
LVCMOS25_8	0b010000	0b001001	0b0000	0b00001	0b11111	0b00001	0b01010	-	-	-	-	-	-	-	-	-	-
LVCMOS25_12	0b010111	0b001111	0b0000	0b00110	0b11111	0b00001	0b01010	-	-	-	-	-	-	-	-	-	-
LVCMOS25_16	0b011111	0b010001	0b0000	0b00001	0b11111	0b00000	0b00101	-	-	-	-	-	-	-	-	-	-
LVCMOS25_24	0b101111	0b011010	0b0000	0b00010	0b11111	0b00001	0b10100	-	-	-	-	-	-	-	-	-	-
LVCMOS33_2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS33_4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS33_6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS33_8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS33_12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS33_16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVCMOS33_24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_4	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_6	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_8	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_16	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVTTL_24	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
PCI33_3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
PCI66_3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
PCIX	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVDCI_15	-	-	0b0000	0b01111	0b00111	-	-	0b00	0b00	-	-	-	-	-	-	-	-
LVDCI_18	-	-	0b0000	0b00000	0b11111	-	-	0b00	0b00	-	-	-	-	-	-	-	-
LVDCI_25	-	-	0b0000	0b00000	0b11111	-	-	0b00	0b00	-	-	-	-	-	-	-	-
LVDCI_33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVDCI_DV2_15	-	-	0b0000	0b11111	0b00001	-	-	-	-	0b011	0b011	-	-	-	-	-	-
LVDCI_DV2_18	-	-	0b0000	0b00000	0b01101	-	-	-	-	0b011	0b011	-	-	-	-	-	-
LVDCI_DV2_25	-	-	0b0000	0b00000	0b11111	-	-	-	-	0b011	0b011	-	-	-	-	-	-
HSLVDCI_15	-	-	0b0000	0b01111	0b00111	-	-	0b00	0b00	-	-	-	-	-	-	-	-
HSLVDCI_18	-	-	0b0000	0b00000	0b11111	-	-	0b00	0b00	-	-	-	-	-	-	-	-
HSLVDCI_25	-	-	0b0000	0b00000	0b11111	-	-	0b00	0b00	-	-	-	-	-	-	-	-
HSLVDCI_33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
HSUL_12_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
GTL	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
GTLP	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL135	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL15	0b100100	0b001010	0b0000	0b01100	0b11110	-	-	-	-	-	-	-	-	-	-	-	-
SSTL18_I	0b010011	0b001000	0b0000	0b01110	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
SSTL18_II	0b111000	0b010110	0b0000	0b00110	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
SSTL2_I	0b001101	0b000111	0b0000	0b00011	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
SSTL2_II	0b100011	0b010100	0b0000	0b00011	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
HSUL_12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_I_12	0b111001	0b001100	0b1000	0b00111	0b10000	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_I	0b011110	0b001001	0b0000	0b01001	0b10111	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_II	0b111010	0b010001	0b0000	0b00011	0b11100	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_III	0b011110	0b011010	0b0000	0b00000	0b10111	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_IV	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_I_18	0b010110	0b001001	0b0000	0b00111	0b10111	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_II_18	0b101011	0b010001	0b0000	0b00010	0b01001	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_III_18	0b010110	0b011010	0b0000	0b00000	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_IV_18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
GTL_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
GTLP_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL12_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL12_T_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL135_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL135_T_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
SSTL15_DCI	0b100100	0b001010	0b0000	0b10101	0b10111	-	-	-	-	-	-	-	-	0b000	0b000	0b000000	0b000000
SSTL15_T_DCI	0b100100	0b001010	0b0000	0b10101	0b10111	-	-	-	-	-	-	-	-	0b000	0b000	0b001001	0b010100
SSTL18_I_DCI	0b001111	0b000110	0b0000	0b10000	0b00011	-	-	-	-	-	-	-	-	0b000	0b000	0b000000	0b000000
SSTL18_II_DCI	0b011010	0b001011	0b0000	0b10000	0b11111	-	-	-	-	-	-	-	-	0b000	0b000	0b010110	0b110100
SSTL18_II_T_DCI	0b001111	0b000110	0b0000	0b10000	0b00011	-	-	-	-	-	-	-	-	0b000	0b000	0b111100	0b011000
SSTL2_I_DCI	0b001001	0b000101	0b0000	0b00011	0b11111	-	-	-	-	-	-	-	-	0b000	0b000	0b000000	0b000000
SSTL2_II_DCI	0b010001	0b001001	0b0000	0b00101	0b01010	-	-	-	-	-	-	-	-	0b000	0b000	0b100010	0b100100
SSTL2_II_T_DCI	0b001001	0b000101	0b0000	0b00011	0b11111	-	-	-	-	-	-	-	-	0b000	0b000	0b100100	0b101000
HSTL_I_DCI	0b011110	0b001001	0b0000	0b10100	0b11110	-	-	-	-	-	-	-	-	0b000	0b000	0b000000	0b000000
HSTL_II_DCI	0b111010	0b010001	0b0000	0b01111	0b11111	-	-	-	-	-	-	-	-	0b000	0b000	0b010111	0b100010
HSTL_II_T_DCI	0b011110	0b001001	0b0000	0b10100	0b11110	-	-	-	-	-	-	-	-	0b000	0b000	0b011110	0b100100
HSTL_III_DCI	0b011110	0b011010	0b0000	0b00000	0b11110	-	-	-	-	-	-	0b10	0b000000	-	-	-	-
HSTL_IV_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
HSTL_I_DCI_18	0b010110	0b001001	0b0000	0b00111	0b00111	-	-	-	-	-	-	-	-	0b000	0b000	0b000000	0b000000
HSTL_II_DCI_18	0b101011	0b010001	0b0000	0b01110	0b01111	-	-	-	-	-	-	-	-	0b000	0b000	0b110101	0b100010
HSTL_II_T_DCI_18	0b010110	0b001001	0b0000	0b00111	0b00111	-	-	-	-	-	-	-	-	0b000	0b000	0b011010	0b100100
HSTL_III_DCI_18	0b010110	0b011010	0b0000	0b00001	0b11111	-	-	-	-	-	-	0b10	0b000000	-	-	-	-
HSTL_IV_DCI_18	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
BLVDS_25	0b101100	0b101100	0b0000	0b00101	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
LVPECL_25	0b110000	0b111100	0b0000	0b00110	0b11111	-	-	-	-	-	-	-	-	-	-	-	-
LVDS_25_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LVDSEXT_25_DCI	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

Table LVDS_DATA

virtex6 table LVDS_DATA
Row	OUTPUT_T	OUTPUT_C	TERM_T	TERM_C	DYN_TERM_T	DYN_TERM_C	LVDSBIAS
OFF	0b000000000	0b000000000	-	-	-	-	0b00000000000000000
LVDS_25	0b100100000	0b000011110	0b000000000	0b100011110	0b000000010	0b100011110	0b10100010101000010
LVDSEXT_25	0b110100000	0b000011110	0b000000000	0b100011110	0b000000010	0b100011110	0b10100010101000010
RSDS_25	0b100100000	0b000011110	0b000000000	0b100011110	0b000000010	0b100011110	0b10100010101000010
HT_25	0b101100000	0b011001110	0b000000000	0b111001110	0b000000010	0b111001110	0b10100010101000010

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